Arm Ltd. has pulled out all of the stops with its new ARM11 micro-architecture, which implements the new ARM6 instruction set. Whether it's SIMD multimedia acceleration, floating point, compact Thumb16 instructions, or even Java, the new micro-architecture does everything. Delivered as IP, ARM11 can include such options as the vector floating-point coprocessor. ARM11 uses a new eight-stage pipeline that supports out-of-order execution. Initial top speed is 750 MHz via a 1.3-µm process. Next-generation 1.0-µm versions should hit 1-GHz speeds.
This micro-architecture continues the ARM family's use of the AMBA bus and retains the low-power operation that ARM is known for. Power consumption is under 0.4 mW/MHz, including cache controllers. Combined with the multimedia instructions, it makes an excellent choice for portable, wireless multimedia devices. The ARM11 memory subsystem improves task switching. It also reduces bus accesses, thereby lowering power requirements.
New load/store exclusive instructions allow more efficient semaphore implementation, making ARM11 well suited for multiprocessor environments. Enhanced exception handling is provided via new vectored interrupt support.
The ARM11 architecture tolerates unaligned data. In addition, a status bit controls big-endian and little-endian operation, enabling the processor to work well with non-ARM processors and DSPs. Overall, the ARM11 offers a significant architectural advance.