Electronic Design

Hardware Scheduling Accelerates Soft Peripherals

Sophisticated peripherals are space eaters. Left unused, they can consume needed power. Ubicom's IP3023 takes a different approach to peripherals.

The IP3023 contains four MII ports and two SERDES (serializer/deserializer) peripherals. These standard peripherals aren't surprising, given the network-oriented target for the IP3023.

What's missing are more conventional interfaces, such as I2C. The chip does have plenty of parallel I/O pins. The trick is to make these pins dance the right way. Ubicom calls these bit banging devices virtual peripherals.

Ubicom extends the virtual peripheral architecture of its prior MCUs into the IP3023, but with a twist. The 250-MIPS IP3023 implements a zero-overhead, hardware task switch with a 10-stage superpipeline architecture. The approach is named the Multithreaded Architecture for Software I/O (MASI). Software tasks implement one or more virtual devices in software. The hardware accelerates this process.

The IP3023 first determines what thread to execute. This is done on every instruction cycle, making it possible to interleave tasks on a per instruction basis. Each task has its own register set, memory, and context on-chip so that it can execute immediately.

The active thread determination utilizes interrupts and I/O pins. As a result, a task can be waiting for an event and start running on the next available timeslot for the thread.

The IP3023 implements hard real-time (HRT) and non-real-time (NRT) threads. The NRT threads can operate in a round-robin fashion when an HRT thread is inactive. A time-slice table permits HRT threads to be allocated in fixed amounts of execution time necessary for predictable performance of communication or DSP algorithms.

The IP3023 core is extremely small, allowing more space to be used for on-chip memory. Its memory-to-memory architecture can take advantage of this memory.

See associated figure.

TAGS: Digital ICs
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