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High-Speed Networks Demand Low-Jitter Clocks

High-Speed Networks Demand Low-Jitter Clocks

Today’s electronic systems require advanced design from top to bottom. Cost and performance optimization is, of course, important in any application, and power-delivery and noise-coupling concerns are more critical than ever. With clock rates increasing and jitter budgets tightening, advanced mixed-signal clocking ICs now move to the front line in attempts to solve these design issues.

In terms of timing signals, clock edges must be accurate. When the clock edge deviates from its ideal position in time, the deviation is called jitter. Each application has a maximum amount of tolerable jitter, but the higher the clock rate, the lower and tighter the jitter requirement.

High-speed applications, such as optical transport networking (OTN), 10-Gigabit Ethernet, Fibre Channel, and 3G HD SDI, have clock periods as low as 100 ps. Some of these applications can only tolerate 10 to 20 ps of total clock jitter before it starts affecting system performance and bit error rates.

Poorly designed clock and oscillator ICs that don’t implement power-supply noise rejection on-chip can easily couple and amplify noise, producing tens of picoseconds of additive clock jitter and undermining system performance. At that point, the system designer has no choice but to track down the source of the noise and minimize its impact. This extra effort increases the design time, component cost, and complexity of the design.

Sources Of Noise

If power-supply noise is a major design concern, multiple sources can be investigated. One is the ripple induced by switching power supplies. Switching power supplies operate by transferring energy from the source to the load through an inductor. Constant charging and discharging at rates typically between 100 kHz and 1 MHz induces ripple that approximates a saw tooth waveform.

The magnitude of the ripple depends on several factors. For example, reducing the equivalent series resistance (ESR) of the load capacitors decreases capacitor parasitic I-R drop and its contribution to the ripple. Increasing the switching frequency may also help, since the period between charge and discharge can be reduced. More elaborate techniques include multi-phase control, which further shrinks the period between charge and discharge.

Any of these techniques may be implemented but can result in cost, board-space, and design-complexity penalties. In practice, minimizing output ripple below 20 mV p-p is a major challenge, especially in high-power systems. However, some networking and computing applications may have ripple that’s as high as 100 mV p-p.

Power-supply noise can also be induced by neighboring ICs. As large digital and analog devices power on and off, drive heavy output loads, or switch wide digital I/O buses, they induce perturbations on the power rail that ripple through the power plane and couple into neighboring subsystems and ICs. For example, one common challenge involves simultaneous switching noise in large FPGAs that contain hundreds of output buffers driving heavy capacitive loads.

If simultaneous switching is a concern, using differential output buffers on large I/O buses, increasing power-supply decoupling, and careful power-plane design with good isolation between ICs are all essential techniques. Each of these practices can help reduce this type of noise, but cost, feature, and design constraints may prevent designers from using any of them.

Ironically, systems that require the best jitter performance tend to contain the greatest amount of power-supply noise. It’s best to select components that provide immunity to this type of noise across a wide spectrum.

Timing Device Power-Supply Noise

Although power-supply noise can be mitigated, attenuating it to zero is practically impossible. Knowledge of how noise impacts the system is critical to determining the level of design devoted to reducing power-supply noise. For clocking circuits, power-supply noise translates into additional jitter, which can occur through several mechanisms.

Traditional crystal oscillators (XOs) are simple circuits that include an inverting amplifier driving a crystal. Due to the simplicity of low-jitter XOs, vendors often overlook the need for power-supply noise rejection. In many cases, the amplifier is designed, tested, and evaluated only in low-noise environments.

Timing devices have oscillators that are primarily analog in nature, and noise easily pulls the oscillators. Such noise will translate to output jitter through modulation of the fundamental oscillation frequency. The more sensitive the oscillator, the higher the modulation will be for a given amount of noise.

Voltage-controlled crystal oscillators (VCXOs) present another problem. Typically, a varactor placed in parallel with the crystal is used to pull the crystal frequency. The varactor introduces a capacitive coupling path from the power rail directly to the oscillator input. Since the oscillator input is at the node of highest gain, even the slightest coupling can affect jitter.

Another fundamental timing circuit is the phase-locked loop (PLL). PLLs are important because they help to multiply frequencies, clean jitter, or synchronize systems. The traditional analog PLL consists of a phase detector, loop filter, voltage-controlled oscillator (VCO), output driver, and feedback divider.

The PLL is a feedback system that requires high-gain circuits. For example, the VCO gain is typically very high, which provides a wide capture range and guarantee lock across all conditions. Inevitably, the high gain increases the sensitivity to external noise. In many cases, a small amount of power-supply ripple can couple into the most sensitive nodes and be amplified to induce very high jitter on the output. Depending on the architecture, the loop filter may also be a point of sensitivity.

Power-supply noise is dominated by deterministic signals that show up as spurs on the timing ICs’ output and the system’s line output. Using a spectrum analyzer is a good way to detect power-supply noise. For example, if the power supply is switching at 300 kHz and the XO output is 156.25 MHz, spurs will be observable at 156.25 MHz ±300 kHz (i.e., 156.55 MHz and 155.95 MHz) with additional lower magnitude spurs at 300-kHz intervals.

Noise-Reduction Fixes

Although there are system solutions to power-supply noise, the best remedy is to use timing components that reject external noise. Novel timing devices employ cutting edge-techniques to provide ultra-low jitter that’s minimally affected by power-supply noise.

For example, Silicon Labs’ DSPLL technology, based on a patented digital-control algorithm, offers the functionality of traditional analog PLLs but with precise digital control. Using digital circuitry, which includes a digital low-noise variable oscillator instead of an analog VCO, reduces sensitivity to analog influences (Fig. 1). Furthermore, on-chip, low-noise regulators boost the isolation from power supply noise, and supplies to digital circuits may have lower voltages than analog circuits, allowing even more regulation from the same external supply voltage and further isolating the most sensitive circuits. 

A simple comparison between a DSPLL-based XO and traditional XO technology underscores the advantage of using all digital techniques and on-chip power regulation in low-jitter timing devices. Take, for instance, the dramatic increase in output clock jitter when 100-mV p-p sinusoidal noise is injected into the XO power supply (Fig. 2).

Sweeping the noise from 100 kHz to 10 MHz and measuring the additive RMS jitter shows that switching noise can significantly degrade the jitter performance of even the highest-performance XOs that lack on-chip power regulation and power-supply filtering. In contrast, DSPLL-based timing devices maintain consistently low jitter operation, even in the presence of significant board-level noise.


In jitter-sensitive applications, power-supply noise sensitivities increase BOM component count and cost and reduce functional design margin. Using advanced technology that’s highly immune to external noise is an effective way to mitigate design problems before they occur.

End-system designers can rely on DSPLL-based XOs, VCXOs, and clock devices to improve power-supply rejection ratio (PSRR) performance up to tenfold over equivalent traditional XOs, even in noisy conditions. This approach saves design time, minimizes complexity, and reduces the need for excessive power-supply decoupling.

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