IAR Embedded Workbench For ARM Cortex Now Provides Speed Optimization

IAR Embedded Workbench For ARM Cortex Now Provides Speed Optimization

Uppsala, Sweden: The new version of IAR Embedded Workbench for ARM from IAR Systems adds speed optimizations that target the ARM CMSIS DSP library and provide general speed improvements when generating code for Cortex-M processors, according to the company.

One of the new features, stack usage analysis, produces a stack usage report with listings of the maximum stack depth for each call graph root. This information simplifies estimates of stack usage. Thanks to a new way of handling inlined assembler statements, users now can place pieces of assembly code right where they are needed in the high-level code, with access to the surrounding C variables. The inlined assembler code can safely reserve private storage.

The Timeline window has been enhanced with a graphical event log for Cortex-M3/M4 users. When analyzing the timing behaviour, designers will be able to place certain macros in the code. When these points are reached during execution, event messages will be sent and appear in the Timeline window. The new Timeline feature also can provide support for creating a stack usage profile over time of an application.

The function profiling window has been enhanced as well, using a function hide mechanism.

Signum JTAGjet, an advanced, real-time, in-circuit debugger for high-end applications, is now integrated in IAR Embedded Workbench for ARM, making it possible to take advantage of the trace capabilities on Cortex-A and Cortex-R devices when debugging complex systems.

IAR Systems

TAGS: Digital ICs
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