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Electronic Design

Interconnects Matter

XMOS recently released its singlecore version of its quad-core XS-G4, the XS1-L1. The XS1-L1 core is the same XS-G4 (see Match Multicore With Multiprogramming). It handles eight hardware-based threads that can be activated by the 64 peripheral I/O pins that have a 10-ns timing resolution. This allows highlevel peripheral interfaces, such as serial ports, to be implemented in software. The software can handle up to 100 million events/s.

Threads can switch on each instruction because each has its own register set so the single-core processor acts more like an eightcore system. Switching also helps power conservation since the chip can switch modes as easily as it switches threads.

This architectural approach is ideal for deterministic, real-time applications such as motor control. It also allows the chip to handle interfaces, such as USB, that would tax other chips lacking hardware support for USB. The XS1-L1 has 400 MIPS to distribute among its chores. DSP support comes in handy for a range of applications.

The XS1-L1 shares most of the architectural features of its quad-core sibling, including the high-speed XLink ports used for external communication between devices. The XS1-L1 has a pair while the XS-G4 has four.

Having fewer XLinks is not much of an issue with the XS1-L1. In fact, they might not be used in many applications that simply take advantage of the single core’s processing power and peripheral complement. On the other hand, a pair of XLinks allows for some interesting designs.

Many distribution applications fit with multiple XS1-L1 or XS-G4 chips. For example, an articulated robot with a large number of servos could dedicate an XS1-L1 to each servo or maybe a pair of adjacent servos (see the figure). The XLink network provides a deterministic communication system.

Not a new approach, CAN-based (controller-area network) microcontrollers are often used for this type of system. CAN provides determinism but it comes up short compared to the XLink throughput and transparency. XLink makes application distribution significantly easier. Likewise, incorporating more processing power at each node allows for more sensor feedback support.

Need another XLink for the XS1-L1 in a daisy chain? Just implement it in software.

The interesting aspect of XLinks is that they do not have to be used with just XMOS micros. There is already an FPGA XLink implementation, and we will have a Design Solution showing how to do the same with a conventional microcontroller. Look for it in our upcoming September 10 issue.

Other micros are less expensive and possibly more applicable to certain tasks. Having an XLink solution brings these chips into the distributed design mix. It is not just a link between an XS1-L1 and the micro but essentially a transparent link to any thread within a distributed network.

The XS1-L1 is priced less than $5. It has a standby power of 15 mW in addition to an active range of up to 200 mW that makes it suitable for mobile or fixed applications. Most XS1-L1 design wins will be using a single chip, though the distributed designs will be more interesting.


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