EE Product News

Memory-Rich DSP Eyes Wireless Infrastructure Apps

Developers of multi-channel communication and networking systems requiring digital signal processing capabilities are the primary market for a new, powerful DSP that carries a whopping 3 Mbits (128K words) of SRAM- reportedly sufficient to eliminate the need for separate external memory chips in most applications. Targeting wireless infrastructure, Internet telephony, high-speed modem banks, network interface cards, and other similar applications, the 24-bit DSP56311 digital signal processor also has on-chip the Enhanced Filter Coprocessor (EFCOP) that processes filter algorithms in parallel with core operation, thereby increasing overall DSP performance and efficiency. A member of the DSP56300 core family of programmable DSPs, DSP56311 also uses a single clock cycle per instruction engine, a barrel shifter, instruction cache, and direct memory access (DMA) controller. It offers 150 MIPS performance (255 MIPS using the EFCOP in filtering applications) using an internal 150-MHz clock, 1.8V core, and independent 3.3V I/O. Two Enhanced Synchronous Serial Interfaces (ESSI), an 8-bit parallel Hot Interface (HI08), and a Serial Communications Interface (SCI) with baud rate generator also are on the chip. DSP56311 comes in a small (15 x 15 mm) 196-pin PBGA scheduled for sampling this September and for production in the fourth quarter.


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TAGS: Digital ICs
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