Arm Cortex-R5 architecture
Arm Cortex-R7 architecture
Cortex-R5 and R7 pipeline
Arm's new Cortex-R5 (Fig. 1) and Cortex-R7 (Fig. 2) are ready for 40nm. These two architectures extend the real time Cortex-R4 architecture released a couple years ago. These higher end multicore processors are designed to tackle a range of applications from automotive to LTE. They will be found were real time, safety and high reliability are critical.
The Cortex-R5 is a 1.66 DMIPS/MHz dual core architecture. The cores can operate in lock step mode where redundant platforms are required such as automotive drive train and safety systems. It includes an optional space saving single precision floating point unit (FPU). It also pushes ECC with single bit error correction onto the internal bus and L1 memories.
The Cortex-R7 cores runs at 2.5 DMIPS/MHz making it almost twice as efficient as the Cortex-R5. The Cortex-R7 architecture (Fig. 3) does this using a deeper pipeline and some out-of-order execution. The latter is limited keeping real time programming in mind. The cores can operate in SMP (symmetrical multiprocessing) and AMP (asymmetrical multiprocessing) mode. The Cortex-R7 also has ECC support throughout. It can tackle higher performance chores like LTE Advanced.
Both architectures can have Tightly Coupled Memories (TCMs) that integrate directly with the processor registers. The Cortex-R7 can also support low latency RAM connected to the data and instruction caches.
Cache coherency is maintained between cores and external I/O with the Cortex-5. The Cortex-R7 also maintains coherency with I/O devices that connect via the AXI Accelerator Coherency Port (ACP).
The Cortex-R7 interrupt can also be optimized for processor throughput or for low latency. This can be applied by core allowing one core to provide maximum throughput while the other handles interrupts. Interprocessor interrupt routing provides fast communication between cores.