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New Core Reduces Code Size In MCU

Compared to the company's current H8S core, the 32-bit H8SX architecture with a CISC CPU core, on-chip multiplier, and a divider promises to reduce code size by 17%. The architecture delivers up to 48 DMIPS and provides a maximum operating frequency of 48 MHz. It includes a 32-bit wide external bus, multiply/divide function, and an optimized instruction set. Easing peripheral connectivity, the architecture also includes a function for converting data to little-endian format and an address/data multiplex bus I/O interface that can be set for each area of an external device. Other features include 87 instructions and 11 addressing modes - an increase of 18 and 3, respectively, compared to the original H8S core. Delivering up to 35 DMIPS, the H8SX/1650 microcontroller (MCU) is the first device to employ the 32-bit H8SX architecture. Features include a 35 MHz maximum operating frequency, a minimum instruction execution time of 28.6 ns, 24 KB of RAM, and a range of peripheral functions. Available in a 120-pin TQFP, price for the H8SX/1650 MCU in sample quantities is $7 each. RENESAS TECHNOLOGY AMERICA INC., San Jose, CA. (408) 433-1990.


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TAGS: Digital ICs
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