Determined to maintain its lead in the DSP world, Texas Instruments continues to expand its product portfolio with a new generation of digital signal processors. These devices promise to deliver an order-of-magnitude improvement in processing power while bringing power consumption to a new low. According to TI, they also should enable a whole new range of consumer and broadband communications applications.
In the advanced very-long-instruction-word (VLIW) arena, TI has extended its VelociTI architecture to create a brand-new, 16-bit fixed-point DSP core. It boasts clocking speeds up to 1.1 GHz and processing performance near 9 BIPS. At this rate, the VelociTI.2-based C64x offers a tenfold improvement over the current flagship DSP core, the C62x (see the figure).
Similarly, the company has developed a superset of the popular C54x low-power, 16-bit, fixed-point core. The C55x DSP core pushes power consumption down to 0.05 mW/MIPS, which is six times less power than its predecessor, the C54x. Plus, it offers a dual-MAC architecture to double the number of instructions per cycle, with a scalable instruction-word length to reduce code size by 30% for optimal memory utilization. Also, the C55x implements new instructions for DSP code parallelism.
Both of the cores are backward-compatible, allowing developers to reuse valuable software code and engineering. The C64x implements increased parallelism and multiple data types to perform many more operations per clock cycle. Ten special-purpose instructions have been added to enhance parallelism. These extensions support quad 8-bit and dual 16-bit operations. And, it employs clever logic techniques to boost speed without using more power. Other features include improved orthogonality, twice as many registers, and 25% code size reduction.
The C55x operates at 400 MHz. To minimize power, the DSP core has advanced power-management techniques that automatically power down inactive peripherals, memory, and core functional units. Also, it provides more buses for greater throughput and more external memory options.
The two new cores are supported by the eXpressDSP development environment and other third-party software. While the C64x is aimed at broadband communications-infrastructure and high-end imaging applications, the C55x targets a new generation of hand-held communications devices.
The first version of these cores will be implemented in a 0.15-µm CMOS process, with plans to quickly migrate to 0.12 µm. Slated for sampling sometime this summer, the C64x will initially run at 700 to 800 MHz. Specific ASIC solutions derived from these cores are expected to be released in the second half of the year.
Texas Instruments Inc., Semiconductor Group, SC-99085A, Literature Response Center, P.O. Box 172228, Denver, CO 80217; (800) 477-8924, ext. 4500; www.ti.com.