Next-Gen CEVA DSP Core Spotlights Native 32-Bit Processing

Adding capabilities and more than doubling the performance of the CEVA-TeakLite core, the CEVA-TeakLite-III third-generation DSP architecture features native 32-bit processing and is backward compatible with previous versions. It includes a 32 x 32 MAC unit to support audio standards such as Dolby Digital Plus 7.1, Dolby TrueHD, and DTS-HD. The architecture features a 10-stage pipeline, allowing the core to reach operating speeds to 425 MHz. Compared to CEVA-TeakLite, performance estimates show it to be four times faster on basic operations and two times better on most popular audio codecs. The architecture is available in various configurations for particular applications. Available now, the CEVA-TL3210 and CEVA-TL3214 are two specific configurations. The CEVA-TL3210 includes coupled memories and direct mapped caches plus AHB bus protocols. The CEVA-TL3214 targets cost-sensitive SoCs based on a TeakLite-compatible X/Y data structure. Another configuration, the CEVA-TL3211 includes a 2-level cached memory subsystem with a memory protection unit and AXI interfaces. This configuration targets single-core embedded applications and will be available in early 2008. CEVA INC., San Jose, CA. (408) 514-2900.