Programmable Engine Runs H.264 Baseline In Full-Duplex Mode

Ever since the first microprocessors surfaced, programmable processors have strived to replace dedicated logic to provide a lower-cost, more flexible solution. In signal processing, the same is true. A programmable solution is preferred if it can meet the application's performance and cost demands. However, due to the real-time nature of many DSP algorithms used in video and audio applications, designers often turn to dedicated DSP functions.

The latest video-compression algorithms, such as MPEG-4 and H.264, require more signal-processing computations than previous algorithms. As a result, they've only been implemented with expensive dedicated silicon solutions. The dedicated chips offer little flexibility if the algorithm changes. A redesign of the chip would prove costly and take many months.

To overcome the performance limitations of a general-purpose DSP and provide a level of flexibility equal to a software-based solution, designers at Cradle Technologies went about turning the CT3400 multiprocessor system-on-a-chip (SoC) into a full H.264/MPEG-4 codec. By combining the SoC and necessary application software, they created a solution that now handles the full baseline profile requirements (30-frame/s Common Intermediate Format (CIF) resolution with a 256-kbit/s transmission rate and full-duplex video and audio).

The software leverages the chip's eight DSP cores, six RISC processors, and a novel 128-pin programmable I/O subsystem targeted at video and imaging applications (Fig. 1). Each DSP and RISC processor core can run at a maximum clock speed of either 230 or 260 MHz (depending on the chip's speed grade). Furthermore, the chip architecture can be scaled upward by adding more DSP and RISC processors for greater performance. It also can be scaled downward by eliminating cores to address lower-cost and lower-performance applications. By mid-2004, the company expects to have software development done on the Main profile version of the standard, which handles 720- by 480-pixel frame sizes versus the 352- by 288-pixel CIF image sizes.

By programming the DSP and RISC engines, system designers can create a software application (firmware) that "maps" the desired function onto the silicon resources while delivering performance levels on par with dedicated silicon (28.2 billion multiply-accumulates/s on 8-bit data at 220 MHz). Thus, the H.264 codec's functions can readily be implemented on the CT3400 (Fig. 2). Previous software releases by Cradle provided multimedia and communications applications that executed on the CT3400.

Because multiple DSP and RISC engines are combined on the CT3400, the algorithms can exploit the natural data parallelism inherent in video and imaging applications. That makes programming easier than it is with very-long-instruction-word DSP chips and custom ASICs. On top of that, the integrated RISC subsystem and flexible I/O structure delivers the system control and implements a full set of Internet-protocol (IP) transport protocols. This permits direct glueless interfaces to the IP network and physical-layer interfaces.

The programmable solution enables designers to implement a complete H.264/MPEG-4 advanced video codec, including a G729AB audio codec, the audio/video synchronization, and the IP transport functions. Software development time for all functions amounts to about 12 months of effort, or about half the time required by a dedicated ASIC solution. Because software defines all of the functions, the codec algorithms and almost all other user features of the chip can be upgraded at any time.

The H.264/MPEG-4 AVC (Part 10) standard was ratified in mid-2003, and many companies expect it to replace MPEG-2. This is mainly due to its ability to achieve high-quality video over IP links and its ability to reduce storage requirements by 50% versus MPEG-2. The standard also includes enhanced error and packet loss resilience that help to enhance the video transfers.

Software-development tools include C-language programming support in the form of an ANSI C compiler and GNU libraries; the company's Cradle C compiler and optimizations; and a real-time operating system from eCOS. Another part of the development software is the Inspector Console, a multiprocessor design/debugging environment that includes a cycle-accurate simulator. The debugger allows each processor to support multiple breakpoints, and bus monitors can count events or stop processors. System-wide symbolic debugging can be done as well. Also available is the RDS3400 hardware development platform, a PCI-compatible card that may be inserted into a PC.

The firmware intellectual property that implements the H.264/MPEG-4 AVC costs $25,000 (source-code). A D1-resolution encoder-only main profile version for the surveillance market, will be available this quarter.

Also on tap this quarter will be a complete package called Hammerhead, which includes the H.264 video codec, the G.729 audio codec, the IP transport packet/stream software for design interfaces, two RDS3400 development boards, two RDS300A audio/visual daughtercards, and two seats of the RDS-SDK development tools.

The kit with complete source code costs $45,000. Designers only need to add memory, physical-layer interface chips, and call control software to create a single-chip video-conferencing or videophone solution.