Now an ECMA standard (ECMA-342), RapidIO is poised to make an impact in embedded environments. It incorporates features like error management and reco-very and support for global shared-memory architectures.
RapidIO is a switch-fabric architecture that offers parallel and serial interfaces. It is designed to be easy to implement even in low-cost FPGAs. RapidIO interfaces are showing up in MCUs and DSPs, although RapidIO isn't expected to be adopted by all processor vendors in the near future. RapidIO peripheral adapters for all popular devices and interfaces, such as Ethernet and PCI, will be available in 2004.
RapidIO runs into most other bus and switch-fabric technologies because of its wide application range. But it doesn't necessarily conflict with technologies like PCI, PCI Express, Ethernet, or InfiniBand. RapidIO works best when handling most of the connectivity between processors and peripherals that are part of one embedded application. Bridges to the other technologies are needed when standard external peripheral interfaces are required. For example, RapidIO could provide the interconnect for an array of DSPs, control processors, and network interface processors, while bridges supply access to Ethernet and PCI devices.
KEEP IT SIMPLE is the hallmark of RapidIO's design. RapidIO comes in 8- and 16-bit parallel forms, as well as a serial form that supports one to four channels. These forms use a low number of pins and require a minimal amount of silicon and firmware to implement the packet protocol. The 8-bit parallel interface requires only 40 pins for bidirectional communication. Thus, RapidIO is easier to incorporate into a design, compared to other interconnects. The hardware interface uses IEEE 1596.3 low-voltage differential signaling (LVDS), which is readily available in most silicon intellectual-property libraries.
The specification starts at 250 MHz specifically to support lower-performance processors, lower-end systems, and less aggressive system design. A RapidIO switch that tolerates different speeds enables high-performance processors to be easily mixed with lower-performance and lower-cost solutions. Parallel and serial RapidIO can also be mixed.
The packet protocol supports read/write transactions up to 256 bytes and messages up to 4 Kbytes. In addition, it handles in-band interrupts and read-modify-write transactions. Spare packet bits enable application-specific transactions.
Things get more complicated when taking on the optional global shared-memory feature. The system allows memory to be distributed among nodes and shared via the RapidIO switch fabric. To keep the overall design simple, domains are used for cache coherence. The design is optimized for domains that contain 16 or fewer nodes.
SERIAL RapidIO provides very low pin counts, making it very useful on the backplane or in pin-limited environments like DSP farms. The lower-performance 1.25-GHz Serial RapidIO speed can be used on legacy backplanes like CompactPCI. This speed can be a tough hurdle to overcome for a processor that only runs at 200 MHz. But the higher speeds are ideal for newer, higher-performance processors. Additional bandwidth can be provided by striping across multiple links.
Unlike InfiniBand and PCI Express, Serial RapidIO specifies the number of lanes or channels using 1x, 2x, 3x, and 4x, not the speed of the channel. Independent of this designation, channel speed ranges from 1.25 to 3.125 GHz. Serial RapidIO uses an error retry and recovery system that's similar to Parallel RapidIO.
At this time, 8-bit parallel and 1-bit serial RapidIO implementations are the most common. RapidIO switches provide a mechanism to link different RapidIO form factors together. The Hardware Interoperability Platform document defines connectors for off-board communication. Also, a new RapidIO Mezzanine Card (RMC) form factor and connector standards are expected soon through the VMEbus International Trade Association (www.vita.com). Additional standards are forthcoming from PICMG (www.picmg.com) for CompactPCI 2.x and Advanced TCA chassis support.