Electronic Design

Sea-Of-IP Design Methodology Delivers Next-Generation System-On-A-Chip Solutions

A design methodology known as Sea-of-IP will enable the creation of complex processor-driven system-on-a-chip (SoC) ICs. Developed by Philips Semiconductors of Eindhoven, The Netherlands, the process will lie at the heart of next-generation high-volume consumer electronics products such as advanced set-top boxes, home networking, and third-generation mobile phones.

Sea-of-IP targets the conflicting requirements of increased system complexity and quicker time-to-market. It elevates SoC design to a true system-level process where fully tested IP blocks are plugged into predefined system architectures. The methodology capitalizes heavily on Philips' CoReUse architectural framework for reusable IP. Also, it leverages the former VLSI Technology's high-level description language integrator (HDL-i) IP generation and delivery and Velocity rapid silicon prototyping (RSP) tools.

"The Sea-of-IP design methodology represents a convergence between ASICs (application-specific ICs), ASSPs (application-specific standard products), CSICs (customer-specific ICs), and CSSPs (customer-specific standard products), with all four types of ICs now being designed using the same re-usable-IP-based approach," says Theo Claasen, chief technology officer at Philips Semiconductors.

"All these designs are based on their use of high-level IP," he continues. "But in addition to having reusable IP, you must also have IP delivery and silicon prototyping tools that put it manageably in the hands of IC designers, advanced semiconductor processes in which to manufacture the resultant SoC solutions in high volume, and attractive pricing."

Building Blocks
IP blocks are the building blocks of SoC solutions in the Sea-of-IP design methodology. Like all blocks, though, they have to fit together easily. Designers must define an architectural framework of bus structures and bus protocols that permit IP blocks to communicate effectively with one another. They also must account for the physical requirements imposed by the semiconductor process that will be used to fabricate the blocks. Testability is a concern as well.

Philips believes the architectural framework required for SoC design will always need to be application-domain specific. In turn, the framework is designed for each of these domains, which are provided by the appropriate Philips Semiconductors Nexperia Silicon System Platform. The latest SoC solutions typically contain a control processor and a DSP, but these items will differ depending on the target application area.

Different IP blocks fit more naturally into some of these platforms than into others. The entire Sea-of-IP design library, however, sits within a single IP repository governed by Philips' CoReUse standards and guidelines. These ensure that every IP block is either inherently reusable by virtue of its design, or is wrapped in a CoReUse-compliant shell. This guarantees sufficient compatibility to allow simple mixing and matching of blocks. Having the entire IP library held consistently within a single IP repository offers an advantage as well. Sea-of-IP logically extends to more traditional ASIC design flows. Users, then, can develop their own system architectures.

The CoReUse program also boasts an internal business model that assigns real monetary value to IP blocks. Assignments depend on the blocks' level of reuse and their CoReUse compliance, thereby providing a real incentive for the production of reusable IP throughout the company. Philips also has set up a dedicated ReUse Shop to broker and promote this IP.

The semiconductor company already has over 250 IP blocks for use with Sea-of-IP. These include compilable cores such as multipliers and adders and barrel shifters. UARTs, FIFOs, memory controllers, and other configurable cores also are featured. So are fixed cores like MIPS and ARM CPUs, Oak and Palm DSPs, phase-locked loops, and analog-to-digital and digital-to-analog converters.

The library includes cores for Philips' TriMedia R.E.A.L. DSP processor and 80C51 microcontroller families, plus components from the Mentor Graphics Inventra library. These are complemented by memory generators for SRAM and ROM, with similar generators for nonvolatile memory and DRAM. Special-function memory modules will soon be added. As a result, designers will have access to the processing power necessary for meeting a wide range of system performance and power-consumption requirements.

Data Available Through A GUI
To deliver its IP manageably into the hands of IC designers, Philips is using HDL-i, the IP generation and delivery tool the company obtained by acquiring VLSI Technology. HDL-i's power lies in its ability to provide IC designers with all the necessary views of each IP block, ranging from simulation models and documentation to complete layout databases. It also gives users instant access to data sheet, licensing, and availability information. By making all this IP-related information accessible via a graphical user interface, HDL-i improves design productivity and shortens design cycles.

Philips is developing a next-generation SoC prototyping system, code-named NAPA (Nexperia Advanced Prototyping Architecture), for Sea-of-IP designs based on its Nexperia platforms. Nexperia Silicon System Platforms group IP together under architectural frameworks that maximize overall system performance. Similarly, NAPA will allow designers to prototype their SoC designs within the same application-oriented platform architectures.

But the volume and complexity of IP blocks in the merged Philips Semiconductors and VLSI Technology libraries make it increasingly difficult to put the entire IP portfolio onto a single piece of silicon. NAPA overcomes this by selecting the natural choice of IP for a particular Nexperia platform. By inserting appropriate bus bridges and high-speed real-time data tunnels, it breaks the IP down into separate CPU, DSP, and peripheral ICs that can be upgraded without compromising system integrity. These ICs are then placed on plug-in prototyping boards that permit the same mixing and matching of CPU and DSP cores as the corresponding Nexperia Silicon System Platform.

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