Electronic Design

Software Directory: ARC International Precise/MQX

Precise/MQX utilizes MMU support to protect code and data areas, but its task architecture doesn't group tasks into higher-level processes. This keeps the real-time operating system (RTOS) compact, letting it be deployed on low-end platforms. A group of tasks may share resources, yet no concept of a process or process-level resource ownership exists. Restricting execution units to tasks doesn't limit Precise/MQX much when it comes to embedded applications since tasks are typically cooperative and statically allocated.

Even though Precise/MQX implements the typical interprocess communication features like semaphores, it's the messaging system that's unique.

The messaging system is queue oriented, and message sends and receives are asynchronous. Asynchronous op-eration minimizes the number of threads needed to handle multiple data streams versus a synchronous system. The mixed-endian support allows message passing to work in a heterogeneous environment.

Each queue is identified by the processor number and a queue number. The underlying transport mechanism provides delivery whether or not the destination queue is on the same processor. An SMP system is considered as a single processor with respect to queues. Although redirection can be implemented, it's not a standard feature of the queue system.

The OS handles memory management for queues. One task owns a message, and ownership changes when a message is sent to a queue. When it's no longer needed, the memory can be released. Private memory pools deliver quick, deterministic message management.

Precise/MQX handles a range of processors including DSPs, making it ideal for GPP/DSP dual-processor SoCs. Tasks can be restarted without being destroyed, and its queue-based message system minimizes task switching.

The Precise/MQXsim simulator allows development to occur even when hardware isn't available. It can also be used in a multiprocessor system using the messaging system to link applications running in the simulator with others running on the hardware.

See associated table.

TAGS: Digital ICs
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