With multiple tools being brought to bear on the process of DSP design and synthesis, the AccelDSP Synthesis 8.1 tool and AccelWare DSP libraries of algorithmic IP make short work of FPGA-based DSP design. This edition of the AccelChip tool and IP package is the first since Xilinx acquired AccelChip in January.
When combined with the System Generator for DSP tool, the AccelDSP Synthesis 8.1 tool gives DSP algorithm and system designers who use The MathWorks’ Matlab and Simulink design tools a very capable design flow for high-end DSP system design.
Included in the tool suite is the AccelChip DSP algorithmic synthesis tool; the M2C Accelerator, which automatically converts fixed-point Matlab code to C++ for faster verification; IP-Explorer technology, which is used for automatic selection of algorithmic IP based on system parameters; and the option to export IP directly into the Xilinx System Generator for DSP tool. The package also includes the AccelWare IP building blocks toolkit.
Tight integration of the AccelDSP Synthesis 8.1 tool with The MathWorks’ model-based design flow helps users overcome the limitations of a document-based development process. In this flow, comprehensive system-level mathematical models replace documents. The models serve as an executable specification that enables users to simulate and explore architectural implementations as many times as needed during the development process. This will ensure that the final implementation meets project requirements.
The AccelDSP Synthesis 8.1 tool is available now for the Windows XP operating system as an option to the Xilinx Integrated Software Environment (ISE) tool. Current AccelChip DSP Synthesis maintenance customers will receive AccelDSP at no cost. Pricing for AccelDSP Synthesis starts at $30,000 for a one-year, floating, subscription-based license. Optional AccelWare IP toolkits cost $5000 each. A composite license for AccelDSP and all AccelWare libraries is available for $40,000.
For information about AccelDSP, visit: http://www.xilinx.com/AccelDSP.