Even when the flexibility and high-level performance of commercial configurable DSP chips come up short, you can still create your own DSP solution using custom ASIC designs or FPGAs. Today, just about every ASIC supplier has a cell library that includes multiplier-accumulator cores, full DSP cores, and other compute blocks needed to implement computational arrays that can execute complex algorithms.
On top of that, third-party IP suppliers such as ARC, ARM, Tensilica, and others can provide general-purpose compute engines with extensions supporting DSP operations. Multiple instances of the cores can then be co-integrated to form a compute array.
In such a case, a control processor or state machine could manage the flow of data through the compute array, as well as manipulate the configuration of the multiple compute blocks. Configuration options can be planned for, and then by using bus switches or crossbar switch fabrics, low-latency connections can be setup to interconnect the compute blocks and memories.
FPGAs, such as those from Actel, Altera, Quicklogic and Xilinx, are also well-suited to host computational arrays of ALUs, multipliers, or other computational blocks. Large arrays of multiplier-accumulators can be configured in the logic. Then, by using the reprogrammable nature of the SRAM-based FPGAs and the programmable interconnect structures, designers can optimize the FPGA configuration each time a different algorithm is needed. This allows designers to reuse the logic and reduce system costs, because the programmable silicon can handle multiple tasks. Altera, for example, has a Web page dedicated to DSP solutions at:
www.altera.com/solutions/dsp/dsp-index.jsp
Xilinx also has DSP support information on its Web site:
http://support.xilinx.com
Whether an ASIC or FPGA, system designers must define the software control and configuration control required to manipulate the logic. Designing such software, however, could end up as a more challenging task than the hardware, because it requires two levels of software that must work in tandem. At the lowest level is the basic control software that performs the signal routing, block configuration, etc., at the silicon level. The higher level is the application software, such as an MPEG decoder or MP3 encoder or H.263 video codec, and so on, that leverages the low-level software to implement the desired signal-processing algorithms.