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Electronic Design

Three Core Micro Pushes Powertrain Performance

Multicore has changed the way designers tackle problems but the automotive space has taken a slower, managed approach. Lockstep pairs of cores has become common but using more cores is not the norm when it comes to safety critical applications like engine control units (ECU). Freescale's latest chip moves in this direction.

Freescale extends its Qorivva line with its new three core MPC5746M (Fig. 1).Three core chips have shown up on desktops and laptops like AMD's Phenom X3 but this approach often takes a four core chip and turns off a core to reduce power requirements or to save silicon. Freescale's new chip is specifically designed as an asymmetric multiprocessor (AMP) platform where one pair of cores runs in lockstep so it is functionally a dual core system where one is very reliable. It targets safety-oriented applications such as automotive.

At more than 300 EEMBC Automark, the MPC5746M deliver twice the performance of the single core MPC5674F. It maintains the same power envelope as the MPC5644A while delivering five times the performance (see 32-bit Micro Targets Powertrain And More).The multicore safety architecture chip is part of Freescale's SafeAssure program. The program is designed to help meet ISO26262 ASIL-D safety integrity functional safety certification.

Freescale's MPC5746M has three 32-bit, e200z4 cores. Two can operate in lock step with a third handling peripheral management.

Figure 1. Freescale's MPC5746M has three 32-bit, e200z4 cores. Two can operate in lock step with a third handling peripheral management.

Freescale's MPC5746M has three, 32-bit, Power Architecture e200z4 cores with DSP support running at 200 MHz. Two operate in lockstep to provide reliable computation with hardware-based redundancy. A third core is designed to handle I/O offloading the main processing pair. The cores have access to 4 Mbytes of flash, four 64 Kbyte EEPROM banks, and 128 Kbytes of RAM plus a number of specialized SRAM memory blocks.

The lockstep cores share a 200 MHz cross-bar switch with Error correction coding (ECC) support. The I/O core has a 100 MHz cross-bar switch.This essentially provides the same bandwidth to all the cores.

The I/O core incorporates FlexRay and Ethernet support. The I/O core also has access to an array of peripherals including LIN, CAN and other serial interfacs. It has a number of timer interfaces. The processors share access to a 60-channel Sigma-Delta ADCs and an 8-channel SAR ADC. The eDMA can has 64-channels and the GTM103 general timer module supports 120 channels.

Safety is key to the MPC5746M's design that includes hardware-based redundancy as well as improved self-test and error correction. The chip supports LBIST (Logic built-in self test) and MBIST (Memory built-in self test) support. ECC is end-to-end and part of the fault collection and correction unit (FCCU). Microcontrollers not targeted at safety-oriented applications often lack these features.

The hardware is backed up with automotive software. This include an AUTOSAR (AUTomotive Open System Architecture)  and the matching microcontroller abstraction layer (MCAL) drivers.The Qorivva family also has extensive third party software support.

Tamper protection is also part of the MPC5746M's design. It provides Flash Reprogramming Detection and Prevention using a Hardware Security Module (HSM) on the I/O core that supports on-chip encryption.

Freescale is delivering a hardware evaluation board (EVB) with a MPC57xx motherboard and a 176 LQFP daughter card. This supports Freescale's Enhanced Calibration (eCal) tools. Freescale is also providing motor control and engine control reference designs.

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