EE Product News

Transceiver Family Readied For OC-48 And OC-192 Marts

Claims of jitter and power dissipation specs far lower than competitive devices are made for a new family of transceiver ICs targeted at OC-48 and OC-192 communication systems. The family embraces five devices: the Si5600 complete transceiver for OC-192 applications; the Si5100 and Si5110 OC-48 transceivers with 1:16 and 1:4 serialization/deserialization paths, respectively; and the Si5540 and Si5530 OC-192 transmitter and receiver ICs for use in designs calling for separate ICs for transmit and receive functions. Jitter performance for the ICs is said to exceed SONET jitter generation, tolerance and max. transfer specs by at least a factor of two. The transceivers dissipate just 1.2W and employ a transmit path that uses a clock multiplier unit (CMU) based on the companyÕs DSPLL architecture. Using digital signal processing to synthesize the analog PLL loop filter function in digital circuitry, the architecture is designed to support two programmable loop filter bandwidths, allowing users to set the CMUÕs jitter attenuation characteristics. The 196-lead BGA Si5600 has a 16-bit wide, 622-Mbps low-speed interface; the 196-lead BGA Si5100 has a 16-bit wide, 155-Mbps low-speed interface that can be pin-strapped to operate as a 4-bit wide, 622-Mbps interface; while the 99-lead Si5110 OC-48 is a 4-bit version of the Si5100. For more details, call Mike Petrowski at SILICON LABORATORIES INC., Austin, TX. (512) 464-9426.


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TAGS: Digital ICs
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