Electronic Design

Two-Level Configurable Compiler Hits Multiple DSP And VLIW Targets

Efficient code generation for DSPs and VLIW processors is a difficult process. So compilers are often created for a particular processor architecture to enable programmers to employ specific features of the architecture. Altium's new Viper compiler framework takes a two-level approach. The compiler can target different processor architectures by providing configuration files that describe an architecture, including features and optimizations. This method offers portability be-tween different target processors. Altium can support additional target processors by simply creating new processor definition files.

Similar to many existing compilers, the Viper compiler framework generates an intermediate code for a virtual architecture. Conventional compilers translate the intermediate code to object code for a particular target.

But the Viper implements two unique intermediate code levels: the medium-level intermediate language (MIL) and the low-level intermediate language (LIL). The MIL is somewhat generic, taking into account target-specific aspects from MIL definition files. The LIL is defined via a target description language (TDL). It addresses features such as instruction scheduling and register allocation. Optimizations for both languages also are supplied in the Map definition files. While the Viper framework is initially aimed at DSP and VLIW processors, the technology is equally applicable to conventional processor architectures.

Compiler optimizations can handle translation of loops into SIMD (single instruction, multiple data) or MIMD (multiple instruction, multiple data) target instructions. Language extensions and target-specific pragmas can also benefit from architectural features of the target. Unfortunately, programmers will still have to be aware of the target architecture to take advantage of some features. For example, proper data alignment is required for many target instructions. Some of these features are handled in a generic fashion through the support of DSP-C language-specific extensions.

On the other hand, compilers tend to be better at register allocation and instruction scheduling that's difficult to accomplish when dealing with complex algorithms. In this type of optimization, the compiler back end can more effectively massage LIL code than MIL code. In addition to target-specific optimizations, the Viper framework applies such classical compiler optimizations as code reordering, tail merging, and strength reduction.

The initial implementation of the Viper compiler framework is Altium's new Tasking StarCore compiler.


TAGS: Digital ICs
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