Labs Investigate New Materials To Boost IC Speeds

Aug. 6, 2001
Scientists at Oak Ridge National Laboratory (ORNL), Motorola Labs, and Pacific Northwest National Laboratory (PNNL) have entered a cooperative research and development agreement to increase the speed of future generations of ICs....

Scientists at Oak Ridge National Laboratory (ORNL), Motorola Labs, and Pacific Northwest National Laboratory (PNNL) have entered a cooperative research and development agreement to increase the speed of future generations of ICs.

Researchers representing the three labs will pursue new materials to overcome a fundamental physics problem that poses a threat to future semiconductor improvements. The labs believe the semiconductor industry's present ability to increase chip computing power while reducing chip size will eventually reach a standstill.

Scientists say the problem lies in the current gate insulating material, a layer of silicon dioxide approximately 35 Å thick. This "gates" the electrons, controlling the flow of electricity across the transistor. The layer must be thinned each time the chip's size is reduced.

At the current rate of progression, industry experts expect that the gate thickness will need to be reduced to fewer than 10 Å in the next 10 years. Yet silicon dioxide with a thickness of less than 20 Å is no longer able to provide effective insulation from the effects of quantum tunneling currents. This inability will cause chips to fail.

Industry experts predict that new materials must be developed with higher dielectric constants for use as effective gate insulators at thicknesses of fewer than 20 Å. These materials must also have a higher capacitance for a given thickness. Working independently, ORNL and Motorola Labs have been developing such materials in the form of crystalline oxides on silicon and other semiconductor materials.

In the first phase of this three-year agreement, details of ORNL's patented crystalline oxide on silicon process will be transferred to Motorola Labs and PNNL. The second phase includes the testing and optimization of the technology. This will ensure that critical performance issues required for alternative gate silicon technology can be achieved.

For more information on this semiconductor project, visit www.ornl.gov, www.pnl.gov, or www.motorola.com.

Sponsored Recommendations

Highly Integrated 20A Digital Power Module for High Current Applications

March 20, 2024
Renesas latest power module delivers the highest efficiency (up to 94% peak) and fast time-to-market solution in an extremely small footprint. The RRM12120 is ideal for space...

Empowering Innovation: Your Power Partner for Tomorrow's Challenges

March 20, 2024
Discover how innovation, quality, and reliability are embedded into every aspect of Renesas' power products.

Article: Meeting the challenges of power conversion in e-bikes

March 18, 2024
Managing electrical noise in a compact and lightweight vehicle is a perpetual obstacle

Power modules provide high-efficiency conversion between 400V and 800V systems for electric vehicles

March 18, 2024
Porsche, Hyundai and GMC all are converting 400 – 800V today in very different ways. Learn more about how power modules stack up to these discrete designs.

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!