Smarter Motor Management

Peter Morris looks at developments in 3-phase brushless DC motor control.

The increasing use of high-current brushless DC 3-phase motors is undoubtedly imposing stringent requirements on drive electronics from both function and safety aspects. Higher operating voltages and gate drive capabilities, as well as better diagnostic capabilities for safety-critical applications, are fuelling the push to smaller geometries and 'smarter' processes and design techniques.

Recent technical developments have made available a 3-phase motor controller that integrates all the circuitry required to control six power NMOS FETs for fractional horsepower motors up to 50 V. The basic techniques of fixed off-time PWM current control and bootstrapped high-side gate drives are enhanced by adding synchronous rectification control, cross-conduction protection and on-chip charge pumps to allow 100% PWM duty cycles. Safety features and diagnostic output prevent inappropriate switching of the power FETs and allow programmable motor spin-down on power loss.

The device, which is shown in Figures 1 and 2, has three half-bridge drive circuits (only one is shown in Figure 1). Each phase has a high- and low-side drive circuit providing the push/pull control to charge and discharge the external FET gates. The low-side gate driver simply runs off the regulated voltage VREG (13V with respect to ground), while the high-side driver circuit supply is bootstrapped up above the motor supply Vbb (Cx is about 12V with respect to the Sx terminal).

It is common practice to add resistors in series with the gates when driving high current FETs in motor drive circuits to reduce slew rates and hence noise, coupling and emission problems. Since this technique increases turn-on and turn-off times, there is a danger that both FETs in a phase could be partially on at the same time during state changes. To prevent the resulting high shoot-through currents, the design provides a turn-on delay circuit which stops either driver turning on until the other has been turned off for a fixed time (dead time), set by an external resistor on the 'dead' terminal. It is up to the user to ensure that this time is sufficient.

Directly sensing the gate voltages would allow an automatic crossover protection scheme to be implemented, but this would add six terminals to the chip. It is also not generally preferred by designers, the dead-time scheme giving more flexibility for system design.

PWM current control is achieved by chopping the highside FET (which also guarantees frequent refresh of the bootstrap capacitor during normal operation). A fixed off-time control scheme is implemented – the user setting the scale (external sense resistor in the bridge's ground return) and the timing (parallel resistor/capacitor on the RC terminal). This fixed off-time function can be used as the main current-control loop or as an upper current limit with the PWM terminal duty cycle providing the main control. To prevent false tripping by reverse recovery spikes, user-adjustable leading-edge blanking is integral with this scheme.

To achieve correct commutation of the three half-bridges requires accurate rotor position information. A way of doing this is via three Hall-effect sensors placed at 120° (electrical) intervals, with their logic outputs being fed to the Hx inputs. Any scheme that provides a clear logic level signal (such as angular position sensors or back-EMF detection) can also be used.

The control logic block takes the commutation information and the fixed off-time signal, together with other user-controlled inputs, to provide the appropriate logic states to all six outputs. Standard control functions of direction, pulse-width-modulation of the active high-side driver, reset and brake are complemented by two more advanced features – operating mode and synchronous rectification (SR).

The mode terminal allows the selection of slow or fast decay modes, which defines the load current recirculation path during the off-time, allowing the user flexibility to
profile the load current waveform. During slow decay, the high-side driver only is turned off, and the current recirculates through the same phase's low side. During fast decay, the same thing happens but, in addition, the low-side driver is turned off so the current also recirculates through the corresponding high-side FET.

The SR input allows selection of synchronous rectification, which turns on the appropriate low- or high-side driver during recirculation, shorting out the reversed body diode and hence reducing dissipation in the power FETs. The body diodes will still be conducting for the duration of the dead time. It is crucial for these types of high-current applications to have protection circuits to prevent inappropriate FET drive signals, as well as general circuit protection.

The process chosen for this device is Allegro's ABCD3 process (Allegro Bipolar/CMOS/DMOS, third generation). Merging analogue bipolar/CMOS, low-voltage CMOS logic and power DMOS transistors, ABCD3 features 65 V vertical power DMOS devices as well as 12, 35, and 65 V lateral DMOS transistors. In addition, it provides several features that allow an efficient die size to be achieved for this design, such as the twin buried layers. One complication is the maximum on-chip gate-source voltage is restricted to 10 V, so the design of several circuit blocks requires care to ensure that no gates are overstressed. Here, ABCD3 helps as there are suitable Zener-diode structures available for gate clamping.

The device is assembled into a standard low-cost 32lead PLCC package.

The requirements of the gate drive circuitry (especially the high-side driver) are very demanding:

  • provide an absolute minimum gate drive of 10 V – for efficient power FET selection
  • minimal static current consumption from the bootstrapped supply, which governs the size of the top-up charge pump
  • operation from a 50 V motor supply (VBB), which means up to 65 V maximum on the bootstrapped supply nodes.
  • keep propagation delays low – target 100-200 ns
  • capable of driving 100 nC and higher FET gate charge.

Of course, all these requirements plus the other necessary circuit functions must be integrated for as low a cost as possible; hence silicon area is at a premium.

Under certain circumstances, the chip is required to maintain one phase state and keep the high-side drive on for long periods of time (100% duty cycle). Maintaining gate drive to the high-side FET is critical for these conditions. As there are no recharge cycles for the boot capacitor, the charge decay (and hence loss of gate drive) must be prevented in some way. The high-side gate-drive circuitry does require a small current draw from the boot capacitor, but even if this was not the case, there would be no way to guarantee that leakage on the Cx node (chip, board, and capacitor) would not eventually create inadequate gate drive. Thus some type of auxiliary top-up circuitry is required.

Previous techniques have used a high-side gate monitor circuit to force a boot-capacitor recharge cycle (turning the high-side FET off and the low-side FET on until the boot-capacitor is recharged) whenever the gate voltage falls below a threshold. This system works well, but the intermittent loss of gate drive (effectively going into a brake mode) is undesirable in some applications.

The method chosen for this chip is an internal low-current top-up charge pump that is active when the high-side FET is turned on (Figure 3). Regulating in the charge cycle has the advantage of avoiding having to sense the voltage on the charge pump output (which can be as high as 62 V nominal) and level-shift a control signal back down. Pumping relative to Vbb avoids large and variable voltage swings on the drain of M1 and hence loss of charge due to parasitic capacitances on this node.

A feature of this chip design is to implement a fairly rigorous set of protection features to ensure that under virtually any circumstance the FET drivers can be protected from fault conditions. These circumstances might include poor set-up (eg dead time too short) and situations that might limit the gate drive in some way, leading to excessive system power dissipation.

Outputs are disabled in the event of:

  • undervoltage lockout – if the 13 V regulated output falls below 9.1 V
  • invalid Hall state: only six of the possible eight Hall states are valid positions; all 0s or all 1s are faults
  • a die temperature of more than 165°C; outputs are disabled until the die temperature cools by 15°C, and then re-enabled
  • a 'short-to-ground' on any phase node – detected if the S node does not get within 2 V of Vbb when the highside driver is turned on. This comparator is disabled until the high-side driver goes into its low current drive state, to prevent false tripping as the drive settles. This fault is cleared at each phase commutation to allow limited operation even with one phase dead. However, if the fault causes the motor to stop before a commutation change, a system reset will be required to clear the fault
  • 'short to supply' faults are effectively dealt with by the main current-control loop
  • inadequate charging of Cboot.

Of course, it would be easy to dream up fault scenarios that would damage any IC, but the target with this design was to cover the likely faults that could occur in real applications. For example, there are no direct current limits on the gate-driver outputs, but in a real application these nodes would have some series gate resistance and would not go 'off board', so a direct short is unlikely. In the event of a power FET becoming damaged and causing a gate short, one of the other protection functions may well come into play. In addition, there are other more standard protection features, including current limits on both VREG and the 5 V logic output.

TAGS: Components
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.