The research community and the EDA industry have a huge opportunity! There is a large and growing EDA tools market for highly complex and high-performance FPGAs sitting in their backyard. But, EDA vendors have completely overlooked it.
The latest Dataquest reports show that more than 40% of designs implemented in standard-cell ASICs in 2003 were less than 1 million gates. Over 75% of the standard-cell ASIC designs had frequencies less than 500 MHz. Current-generation FPGAs with capacities of up to 2 million gates and maximum frequencies up to 500 MHz can accommodate most of these designs.
The 300-mm wafer fabs have also helped improve the FPGA pricing structure. On the other hand, prolonged time-to-manufacturing, risk of respins, high inventory costs, yield, signal integrity, and verification issues have plagued the standard-cell ASIC industry. Unless power usage is particularly critical or production volumes are extraordinary, it is usually difficult to justify the expense of ASICs. To this end, more ASIC designers are turning to FPGAs for their production designs.
Of course, with progress comes new challenges, and subsequently opportunities arise. Traditional FPGA tools are very well suited for the majority of designers. However, due to the increasing number of gates in high-end FPGAs, design problems once limited to ASICs are now beginning to surface. FPGA designers are encountering the problem that ASIC designers know all too well—difficulty in reaching and maintaining design closure. When forced to get the design out the door to make the market window, high-end FPGA designers usually sacrifice functionality or usage of the chip. The result is a gap between the number of programmable transistors available and the average number of transistors used by FPGA designers. This "productivity gap" will widen if the EDA community does not respond.
EDA vendors serious about helping designers reduce cycle time and reach performance goals must migrate well-tested, proven ASIC-style methodologies to the FPGA world. These methodologies could fit seamlessly into existing FPGA design flows, enabling designers to address complex design issues at the point of maximum impact. An ASIC-style design methodology could provide designers with early analysis and planning of their designs to maximize performance and avoid lengthy and repeated iterations. It could also provide powerful incremental and modular design capabilities to easily accommodate routine design changes and ease the reuse of intellectual property across multiple designs.
An ASIC-style methodology would provide a representation of the final design early in the design cycle to avoid potential implementation problems. With the intuitive feedback afforded by this approach, designers can quickly visualize and correct problems, such as routing congestion, before they occur. They can also rearrange blocks or physical hierarchy to reduce congestion and interconnect length for higher performance. This type of methodology will additionally reduce overall place and route time and shorten routine design changes or engineering change orders.
Interconnect delays dominate the gate delays in the FPGA fabric. The problem is akin to what the ASIC designers face in their efforts to control route delays to within a few picoseconds. Physical synthesis, which combines the logic optimization step with placement and routing, has been made available to the ASIC community. While similar technologies have started to migrate into the FPGA domain, physical synthesis tools need to mature and move up the adoption curve with high-end FPGA designers.
Mature and robust EDA tools from FPGA vendors and EDA vendors alike would further bolster the FPGA industry. FPGAs already provide a compelling time-to-market advantage over ASICs, and advanced tools targeting the needs of high-end FPGA designers would help establish clear leadership.