Electronic Design

Convert C Code To FPGA Hardware With A Click Of The Mouse

The Nios II C-to-Hardware Acceleration (C2H) Compiler from Altera greatly simplifies the job of accelerating functions in a C program using hardware (see the figure). It also simplifies the chore of linking the instruction stream with the new hardware.

The first step is to identify the function or functions that should be accelerated via software profiling tools commonly used by software developers. A small fraction of a program typically is responsible for the majority of execution time. Consequently, optimizing that fraction can result in significant acceleration. Of course, optimizing an idle loop doesn't provide this type of payoff. Developers, then, should determine which functions should be optimized.

The next step is relatively easy. The developer clicks on the functions that are to be run through the C2H compiler. The compiler is integrated with Altera's Quartus II SOPC Builder and the Eclipse-based Nios II integrated development environment (IDE) so the results of the compiler are ready for integration with the project containing the NIOS II soft processor. Calls to any top-level functions are changed so the new hardware is used instead of calling C code. The C2H compiler walks the function tree so it will optimize called functions, but the compiler doesn't support recursive functions.

Top-level converted functions can be configured so the calling C program will wait until hardware processing is complete. Alternatively, a task-oriented definition permits hardware processing that runs concurrently with an application. The compiler supports the high-bandwidth Avalon interconnect fabric.

Developers then can profile the resulting hardware/software combination to see how much improvement is attained. It's possible to achieve one order or even two orders of magnitude improvement depending upon the application. Switching back to software or adding new functions to compile to hardware is just a mouse click away.

This approach significantly reduces development time. It also reduces errors due to conversion between software and hardware. The compiler output is comparable to what a very good hardware designer can achieve.


TAGS: Digital ICs
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