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Electronic Design

Cost-Conscious FPGAs Quadruple Logic Density

Nearly four times the logic density of previous low-cost FPGA families—that's the earmark of the just-released Cyclone FPGA family. With a logic architecture redesigned from the ground up, Altera now can price the logic at about $1.50 per 1000 logic elements, which is close to half that of competing low-cost FPGAs. As a result, system designers can use FPGAs in systems that once considered standard cell or custom chips the only cost-effective solution.

Initially, four members in the Cyclone FPGA family will be fabricated on a 0.13-µm copper interconnect CMOS process. The chips will range in density from 2910 to 20,060 logic elements and from about 60 to 300 kbits of on-chip SRAM. The basic logic elements let functions such as a 32-bit accumulator operate at 304 MHz and a 32- by 32-bit multiplier-accumulator run at 50.5 MHz. The internal SRAMs have an access time of 5 ns and can operate at 200 MHz.

User I/O pads start at 104 for the smallest FPGA, the EP1C3, and peak at 301 for the largest member, the EP1C20. The I/O lines boast programmable drive strength, bus-hold capability, programmable slew rates, and a hot-socketing ability. Interface options for the single-ended I/O pads include LVTTL, LVCMOS, PCI, SSTL-2, and SSTL-3. Each chip also contains low-voltage differential-signaling (LVDS) channels to handle high-speed I/O applications—the smallest FPGA has 34 channels, while the largest packs 129 channels. Each LVDS channel handles data rates of 311 Mbits/s. The chips also include a memory controller that can handle SDRAM and fast-cycle DRAMs at bus data rates of 266 Mbits/s.

Prices for the FPGAs in 2003 will range from $7 for the smallest device to $60 for the largest, both in volumes of about 50,000 units.

Altera Corp., (408) 544-7000;

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TAGS: Digital ICs
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