Electronic Design

EDA: Tradeoffs Abound In FPGA Design</A><BR><FONT CLASS=body11>Sponsored by: <A HREF="http://www.mentor.com" TARGET=_blank CLASS=body11>MENTOR GRAPHICS</A></FONT><A>

Understanding device types and design flows is key to getting the most out of FPGAs.

Field-programmable gate arrays (FPGAs) arrived in 1984 as an alternative to programmable logic devices (PLDs) and ASICs. As their name implies, FPGAs offer the significant benefit of being readily programmable. Unlike their forebearers in the PLD category, FPGAs can (in most cases) be programmed again and again, giving designers multiple opportunities to tweak their circuits.

There’s no large non-recurring engineering (NRE) cost associated with FPGAs. In addition, lengthy, nerve-wracking waits for mask-making operations are squashed. Often, with FPGA development, logic design begins to resemble software design due to the many iterations of a given design. Innovative design often happens with FPGAs as an implementation platform. But there are some downsides to FPGAs as well. The economics of FPGAs force designers to balance their relatively high piece-part pricing compared to ASICs with the absence of high NREs and long development cycles. They’re also available only in fixed sizes, which matters when you’re determined to avoid unused silicon area.

What are FPGAs? FPGAs fill a gap between discrete logic and the smaller PLDs on the low end of the complexity scale and costly custom ASICs on the high end. They consist of an array of logic blocks that are configured using software. Programmable I/O blocks surround these logic blocks…

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TAGS: Digital ICs
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