With FPGAs pushing aside ASICs in many complex designs, the limits of traditional FPGA timing-analysis tools are being stressed to the breaking point. So if you want to use today's high-end FPGAs in place of ASICs, you'll need to use ASIC-like tools and measurement parameters.
Enter Version 6.0 of Altera's Quartus II design software, which now offers native support for the Synopsys Design Constraints (SDC) timing format. Quartus II v.6.0 incorporates Altera's TimeQuest timing analyzer, which lets users create, manage, and analyze designs with complex timing constraints.
The tool also will handle clock-multiplexed designs and source-synchronous interfaces. Through use of SDC timing formats, users will gain more finely tuned control over timing constraints and achieve faster design closure.
Additionally, Quartus II offers new expandedfeatures in support of team-based design. The software now includes a project-manager interface for managing resource and timing budgets at the design's top level. That interface also enables designers to manage timing constraints between blocks to maximize performance.
Support for SystemVerilog design constructs has been added as well. Through use of SystemVerilog, FPGA designers can achieve RTL implementation in less time than with older Verilog versions.
Both the subscription and Web editions of Quartus II version 6.0 are available now. Annual subscriptions cost $2000 for a nodelocked PC license. The Web edition, which does not include the TimeQuest timing analyzer, is freely downloadable from Altera's Web site.