Electronic Design

FPGA Design Tool Suite Shortens Runtimes And Facilitates Incremental Design

FPGAs are getting larger and larger, as evidenced by Xilinx's Virtex-5 devices, which are produced on a 65-nm process. Designers want faster runtimes for their FPGA tools as well as other features that let them reach timing closure more rapidly.

Version 9.1i of Xilinx's Integrated Software Environment (ISE) offers those runtime improvements, along with what the company calls "SmartCompile technology," which offers a further runtime boost. In addition, SmartCompile allows exact preservation of unchanged logic while revised logic is incrementally recompiled.

Overall runtimes for complex designs are reduced in ISE 9.1i by up to 2.5 times. But SmartCompile adds features such as SmartPreview, which permits pause-andresume functionality in the place-androute process to help identify timing-critical design regions.

Another feature, SmartGuide, works closely with synthesis tools to ensure the use of consistent, repeatable names when resynthesizing small logic changes. As a result, reimplementation runtimes average from two times to four times faster.

A third new feature under the SmartCompile umbrella is Partitions, which enables users to freeze the implementation of specified blocks within a design. These blocks are preserved down to the routing level. Yet another 2.5-times average runtime boost is garnered from Partitions when reimplementing portions of a design.

ISE 9.1i is available now. Prices start at $2495. A full-featured, 60-day evaluation version is available for free. All versions support Windows 2000 and XP, Linux Red Hat Enterprise 3.0 and 4.0, and Solaris 2.8 and 2.9.

Xilinx Inc.

TAGS: Digital ICs
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.