ASIC designers were, at one time, the uncontested heavyweight champions of the electronics design community—the top of the food chain. Their chips were much larger and difficult to design and verify, and they invested with abandon to solve
every emerging methodology bottleneck. EDA vendors were omnipresent, pandering to their every whim. By comparison, FPGA designers were the welterweight champions, stealthily bobbing and weaving their way to victory, all the while revolutionizing future electronics design. They overcame myriads of methodology problems largely on their own with no thanks to the EDA industry, which largely turned its back on this silent majority.
Now the tables have turned. The complexity and affordability of high-end FPGAs makes them the ideal choice for a majority of electronics products that previously were strictly in the domain of ASICs. Each year, ASIC design starts decline. But the number of FPGA design starts is two full orders of magnitude greater, and continuing to climb.
ASICs were once required when performance was paramount, but performance is no longer such a large differentiating market factor. Few can detect if one consumer device takes a few nanoseconds longer to respond to a button push than another. ASICs were also necessary when functionality was the key differentiator. However, once functionality reaches a certain threshold, more just makes devices complex or awkward to use. Last year, we witnessed the absurdity of a refrigerator with a built-in Web browser!
It is high time that the EDA industry took notice of the neglected FPGA design community. FPGA designers still largely use archaic EDA tools, created when flattened designs were still fairly easy to manage.
UPDATE FPGA TOOL FLOWS
Today's FPGA complexity means heavyweight challenges for FPGA designers. They have nearly all the same problems as traditional ASIC designers and thus need new heavyweight EDA tools. Designing multimillion-gate FPGAs without hierarchical EDA tools is like offering your ear to Mike Tyson!
Outdated FPGA tools can delay, obstruct, or even prevent designers from completing their designs. Designers have trouble achieving performance goals, as well as with routing congestion, unpredictable routing results, routing around large logic or memory blocks, and fitting their logic into devices that meet their production volume requirements. Fixing these problems using today's tools typically involves frequent design iterations, a time-consuming process because the tools operate on the entire flattened design.
To attack these problems, ASIC-like floorplanning is required. Floorplanning between synthesis and physical design enables designers to analyze, visualize, and fix potential problems prior to place and route. This greatly reduces the number of design iterations.
In addition, FPGA design tools must be block-based or hierarchical. Designers need an incremental way to change parts of the physical design while leaving those parts of the design that already meet performance goals untouched, rather than re-implementing the entire chip. This greatly shortens iteration time.
FPGA routing can be unpredictable, particularly when applied to an entire flattened netlist. The answer is an incremental methodology that affects only those portions of the design requiring changes. In addition to significantly slashing iteration time, hierarchical design flows provide a teamwork-friendly environment that lends itself to divide-and-conquer approaches.
The new heavyweights of electronics design, FPGA designers face the same challenges as traditional ASIC designers. Let's all hope that EDA vendors will now wind up and provide that knockout punch.