FPGA Embeds 64-bit Cores And High Speed Interfaces

FPGA Embeds 64-bit Cores And High Speed Interfaces

Altera delivered its FPGAs with dual core, Cortex-A9 processors (see Dual Core Cortex-A9 With ECC Finds FPGA Home) a number of years ago and has refined it every since. It has had some competition with Xilinx Zynq (see FPGA Packs In Dual Cortex-A9 Micro). These platforms address the ever increasing demand for more processor performance coupled with an FPGA fabrics.

Altera's latest announcement pushes well past this initial integration raising the FPGA/hard core combination to new heights. The new, 1 GHz Stratix 10 (Fig. 1) will not only be manufactures using Intel’s 14-nm Tri-Gate process (see Moore's Law Continues With 22nm 3D Transistors) but it will include four 64-bit ARM Cortex-A53 cores (see Delivering 64-Bit Arm Platforms).

Figure 1. The Stratix 10 FPGA will be available with a quad core, Cortex-A53 subsystem.

The Cortex-A53 is the low power version of the Cortex-A50 family that also includes the Cortex-A57 designed for high performance. That is not to say that the Stratix 10 will not be targeting high performance applications but rather the FPGA fabric will provide the heavy lifting while the Cortex-A53 delivers the programmatic support needed for the latest high performance applications. For example, the FPGA DSP support can deliver over 10 TFLOPS.

The Stratix 10 will be an interesting platform for Altera's OpenCL support as well (see How To Put OpenCL Into An FPGA). The quad cores provide an environment for programmers while the OpenCL support does the same but limits the exposure of the developers to the underlying FPGA programming complexity.

As with the Cortex-A9 FPGAs, the Stratix 10 cores operate independently of the FPGA fabric although it has tight ties with it. This includes virtualization and error correction code (ECC) memory support. This includes access to up to 256 Tbytes of memory and on-chip L1 and L2 caches. ECC support is critical to enterprise, safety and security related applications. An upgrade path exists since the 64-bit cores can run in 32-bit mode like the Cortex-A9.

The new FPGA family is supported by Altera’s SoC Embedded Design Suite (EDS). EDS is integrated with ARM's Development Studio 5 (DS-5) Altera Edition toolkit. This supports FPGA-adaptive debugging (see Unified Debugging Arrives On New FPGAs With Dual Cortex-A9 Cores). The OpenCL support is part of Altera’s software development kit (SDK) for OpenCL. Conventional FPGA development tools include Altera's Quartus II and DSP Builder.

The Cortex-A9 FPGAs will still be needed but this latest crop of Stratix 10 FGPAs moves the platform into new areas like data center computing and networking as well as applications such as radar where high performance FPGAs already dominate. The addition of the 64-bit cores simply makes the job easier.

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