In the "old" days, the decision to go with ASICs or FPGAs was straightforward. If you needed 20,000 gates or less, required only a few devices, and determined that frequency wasn't an issue, then FPGAs were the obvious choice. For anything else, you used ASICs. Today, ASIC designers must seriously look at FPGAs as a viable alternative in both small and large designs. FPGA vendors have launched a two-pronged attack on the ASIC market by providing two distinct families of parts: one focusing on low cost, and the other targeting capacity and performance.
If product volumes are less than 70,000 units, low-cost FPGAs and complex programmable-logic devices (CPLDs) present a cost-effective alternative to ASICs. Smaller die sizes are providing significant cost savings and driving prices down. Programmable-logic vendors once lagged behind the ASIC market by as much as 18 months when it came to migrating to improving wafer processes. This resulted in higher costs and less-than-optimal performance. Today, those vendors are leading the way.
During the past two years, FPGA devices were used to employ several new deep-submicron wafer processes. This turnaround has resulted in increased performance, lower power requirements, and higher yields. As a result, FPGAs are now showing up in a number of low-power handheld applications such as MP3 audio players and in commercial products like set-top video box switches. With prices now around $2.00 in volume shipments, these relatively risk-free parts continue to be designed in, while small ASICs are being designed out.
The new generation of million-gate-system FPGAs is making inroads into larger designs. Previously, this was an ASIC-only market. Designers turned to these devices primarily for prototyping and as a risk-free alternative to high nonrecurring engineering (NRE) costs. But as mask costs continue to rise to upwards of $250,000 and the average ASIC design start is still around 500,000 gates, many companies are rethinking their ASIC design practices. For the first time, FPGA gate density has exceeded the sweet spot of the ASIC market, and it continues to grow. High-density FPGAs were once considered only for prototyping. Now they're being shipped in production units and in volume.
As ASIC designers shift to FPGAs, EDA companies must provide design tools that migrate ASIC-like design methodologies into FPGA tools and design flows. Design houses are in search of versatile solutions with integrated design flows for small FPGAs. They're also seeking a modular design methodology for teams designing large FPGAs.
To attract ASIC designs, many FPGA vendors are providing soft and hard cores to enable ASIC-type performance on key interfaces and processors. However, intellectual property (IP) in FPGAs is breaking the traditional pushbutton approach of FPGA design by requiring bottom-up techniques found in traditional ASIC tools. As this practice continues, flows and methods to protect IP will become increasingly important, along with EDA solutions that provide easy integration of the IP.
To facilitate the ASIC migration, EDA vendors have begun partnering with FPGA vendors to pioneer new methodologies that go beyond the pushbutton approach. They're focusing on cutting design times and increasing performance to enable more ASIC designs to be completed in FPGAs. Incremental synthesis and in-place optimization, two recent FPGA-design innovations, enhance user productivity and enable focused performance optimization late in the design process while maintaining current placement, area, and noncritical timing.
As FPGAs continue to follow Moore's Law, ASIC replacement will become a more viable alternative. System-on-a-chip designs will migrate to the system on a programmable chip. Toward that end, EDA and FPGA vendors must continue to focus on integrated flows, innovative methodologies, and advances in silicon to support what was once an ASIC-only market.
Contributed by Tom Feist, vice president of marketing, Exemplar Logic.