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Wireless Systems Design

FPGA Prototyping Tool Aligns With ASIC Flow

This FPGA-Synthesis Tool Offers The Prototyping Capabilities Required By RF-Intensive Systems And A Migration Path To ASIC Product Design.

Over a third of all high-end ASIC designers now use FPGAs for prototyping 500,000-plus-gate designs. Driving this trend is the fact that a median application-specific integrated-circuit (ASIC) design can now fit onto the largest field-programmable gate array (FPGA). The one-to-one relationship between these two design platforms has made it easier for designers to test out a complex ASIC design on a single FPGA.

While many tools perform FPGA synthesis, few offer a direct migration path between the world of FPGAs and ASICs. One exception is Synopsys' recently announced Design Compiler FPGA (DC FPGA) software design tool. This tool builds on the success of the company's Design Compiler for ASICs tool suite. It also incorporates the new Adaptive Optimization technology.

Engineers use FPGAs to test out their designs before committing them to silicon for production. As a result, they need an FPGA flow that complements their existing ASIC design environment (see figure). DC FPGA claims to meet this need through its tight integration with the company's ASIC synthesis tool. Specifically, DC FPGA works well with the ASIC flow by accepting the same RTL code, constraints, scripts, and IP libraries as Design Compiler. Furthermore, DC FPGA provides the same interfaces to Synopsys' Formality formal-verification tool as those that are found in Design Compiler. This tight link between synthesis and verification is critical. It enables information about synthesis-optimization techniques to be passed directly to the verification tool.

Today, few tools support formal verification in FPGA designs. In the ASIC world, formal verification and equivalency checking are well-known error-checking techniques. But such tools aren't yet as robust in the FPGA arena. Here, engineers typically verify FPGA designs in a laboratory environment. Without a proven method to verify the netlist against the actual RTL, complete verification of the design may not be possible.

Many current FPGA synthesis tools boast of a "push-button" capability for design synthesis. This automated approach is fine for straightforward designs. But if the results aren't acceptable, the only recourse left is to change the RTL code—a time-consuming task.

In contrast, DC FPGA provides several ways for users to customize the synthesized results. For example, designers can use extensive constraints, commands, and scripts. The company claims that DC FPGA has 10 times the number of available constraints when compared to a typical FPGA synthesis tool. In addition, users can create point-to-point constraints in which certain paths or cells in the design can be fully constrained.

Improvements in algorithmic selection are another benefit offered by DC FPGA. In general, the synthesis process consists of running a collection of 40 to 50 synthesizing algorithms. Most synthesis tools run all of these algorithms—with fixed parameters—in a certain order. Not all of the algorithms will result in a beneficial design. Some may even have a negative effect on a given design (e.g., by not meeting a particular frequency's run-time target). DC FPGA's Adaptive Optimization technology can statistically predict the best algorithms to run for a given design.

These parameters might include, for example, how circuits are hooked up to one another as well as circuit area, circuit speed, and other constraints. Based on these parameters, Adaptive Optimization selects the most appropriate synthesis algorithms. Because DC FPGA doesn't need to run all of the available synthesis algorithms, there is more time to fine-tune the parameters for the algorithms that are run.

Another benefit that is derived from the Adaptive Optimization technology is the ordering of the algorithms. The selected, optimal algorithms don't have to be executed in a particular order. The designer is free to reorder the sequence as desired, thereby alleviating potential "minima" problems. When those problems arise, algorithms with negative results cause the synthesis process to stall. Avoiding these synthesis ruts can lead to better design performance. Plus, the amount of run time that's required for synthesis can be greatly reduced. The company claims that the timing performance can be improved by 15% over traditional FPGA synthesis techniques.

The Design Compiler (DC) FPGA software design tool is currently available. A standalone license starts at $36,750 for a one-year technology subscription license (TSL). Existing users of Design Compiler may purchase an add-on DC FPGA for $19,600 for a one-year TSL.

Synopsys, Inc.
700 East Middlefield Rd., Mountain View, CA 94043; (650) 584-5000,

TAGS: Digital ICs
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