FPGAs Approach Wire-Speed Performance

Thanks to their NetFPGA architecture and a process shrink to 0.25 µm, the DY8000 family of FPGAs is said to enable designers to achieve wire-speed performance in OC3, Gigabit Ethernet, ATM and 66-MHz PCI applications. The new FPGAs offer 21 programmable I/O levels selectable on a pin-by-pin basis, which gives users more flexibility to interface to a wide range of signal levels without translators. They also offer differential capability on adjacent I/O pins for maximum noise immunity in high-speed systems.The FPGAs pack up to 6272 logic cells in an architecture that results in interconnect performance improvements of up to 75% over the earlier DY6000 family.