New FPGAs from Altera and Xilinx have hit 40 nm and continue to push the performance envelope.
The stratix Iv line from Altera comes in enhanced (E) and transceiver-based (GX) versions. the top end of the GX version supports 48 channels operating at speeds up to 8.5 Gbits/s. the chips incorporate four hard cores that support up to x8 PCI Express Gen 2 in addition to other standard interfaces such as serial RapidIo and Gigabit Ethernet. Also, the chips can handle DDR3 memory interfaces and include on-chip termination.
The FPGAs can have up to 680k lookup tables (LUts) along with 22.4 Mbits for RAM and 1360 embedded 18-by-18 multipliers. Altera’s Programmable Power technology allows logic blocks to operate at different speeds, potentially reducing power requirements by as much as 50%.
The latest Quartus II and soPC Builder development environment supports the chips. this version also handles the latest features such as power conservation with its PowerPlay Power Analysis tool.
Xilinx’s virtex-6 40-nm FPGA complements the company’s low-cost, 45-nm spartan-6 FPGA. Xilinx created the virtex- 6 using a triple-oxide, 12-metal layer process on 300-mm wafers. the chips can cut power requirements by 50% compared to their older counterparts while costing 20% less. the virtex-6 is available in 1- and 0.9-v core voltage versions.
Additionally, the virtex-6 comes in three flavors: the LXt with DsP and serial connectivity, the higher-performance sXt, and the HXt, which adds hard-core, 11-Gbit/s serial interfaces with DDR3 support. the family supports up to 760k LUts, 38 Mbits of RAM, and 2000 DsP slices. the virtex-6 will have EasyPath support that is a low-cost alternative to AsIC migration for virtex-6 designs.
The spartan-6 uses a nine-metal-layer, dual-oxide process and the new dual-register, six-input LUt logic. It’s available in LX and LXt versions. the LXt adds hard-core serial interfaces including DDR3 support. the Xilinx targeted Design Platform sports the latest spartan-6 FPGA (see the figure).