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FPGAs Raise Integration Bar

Fabricated on Fujitsu’s 90-nm CMOS process technology utilizing 300-mm wafers, the LatticeSC FPGA family squeezes I/O, SERDES, structured ASIC blocks, and FPGA fabrics on a single chip. The devices provide up to 32 SERDES channels, each running at rates from 600 Mb/s to 3.4 Gb/s. For backplane applications with drive lengths approaching 60", users can enable the transmit pre-emphasis and receive equalization features built into the SERDES. Power consumption is 100 mW per channel at 3.125 Gb/s and jitter specifications at 3.2 Gb/s are 0.29 UI for total transmit jitter and 0.8 UI for total receive jitter tolerance. The devices include a flexiPCS block, configurable to support popular data protocols including PCI-Express, 1.02 or 2.04 Gb/s Fibre Channel, Gigabit Ethernet, 10-Gigabit Ethernet, Serial RapidIO, and SONET. Other features include a FPGA fabric capable of 500-MHz performance and 1 Mb to 7.8 Mb of embedded block RAM, also capable of 500-HMz operation. Design support for the devices comes by way of ispLEVER Version 5.1 Service Pack 2 design tool suite, which includes simulation and synthesis support from Mentor Graphics and Synplicity. Available in 2007, pricing for a basic LFSC25 in a 900 fpBGA package is $49 each/25,000. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000.


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