Electronic Design

Incremental Compilation Comes To FPGA Design

Today's FPGAs are large--really large. The largest are closing in on 200,000 logic elements and include features like memories, analog phase-locked loops, transceivers, and more.

Yet that complexity cuts two ways. It lets FPGAs compete with ASICs for design starts, but it also makes for long runtimes for FPGA design tools. That "but" is a thumb in the eye of FPGAs' main attraction for designers, their reprogrammability. The sheer size and complexity of FPGAs is beginning to make design with them an inefficient process.

In version 5.0 of its Quartus II design software, Altera takes dead aim at FPGA design efficiency with an incremental compilation feature. This allows designers to break their designs into physical and logical partitions for synthesis and for fitting to the FPGA's sea of gates.

These partitions are maintained through synthesis iterations, so only the segments that have seen design changes require recompilation. Compile times can be reduced by up to 50%, and as a result, a design can see four or five iterations a day instead of only one or two.

Designers can apply different optimization techniques to different partitions for purposes of timing closure. Furthermore, a graphical user interface makes partition setup relatively easy to accomplish. However, all parts of the Quartus II suite support script-driven operation.

Extensive documentation is provided, including design examples of partitioning. The documentation also makes recommendations regarding whether partitioning should or should not be used. It doesn't necessarily make sense for all designs, especially smaller ones.

Both the subscription and Web editions of Quartus II 5.0 are available now. The Web edition is freely downloadable now. Annual subscriptions for the full suite cost $2000 for a node-locked PC license. The tool supports all of Altera's FPGA families, including the high-density Stratix II devices.

See associated figure

Altera Corp.

TAGS: Digital ICs
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