Amultidrop version of SAE AS5652—the 10-Mbit/s version of MIL-STD-1553—will soon appear in more nextgeneration avionics applications. Typical applications for MIL-STD-1553, a proven 1-Mbit/s bus technology, include navigation systems, communications systems, and weapons systems.
Areas unknown to MIL-STD-1553, such as low-level flight control, now have a perfect fit with the multidrop version of SAE AS5652. Low-level flight controls generally include sensors, actuators, controllers, and power-management systems requiring typical refresh rates around 1000 Hz, which is much too fast for MIL-STD-1553.
SAE AS5652 also is known as EBR-1553. While MIL-STD-1553 uses a drop bus, SAE AS5652 has a star topology hub. It uses the same protocol as MIL-STD-1553, but with a tenfold improvement in data rate. As SAE AS5652 goes through its widespread adoption into weapons systems, a drop-bus version presumably to be called AS5652A will bring a much wider application base.
The drop-bus version also could very well bring standardization to low-level flight control, which uses more than 40 different data links that mostly are RS-422/485 point to point. Similar to other flight-control data links, AS5652A will employ RS-485 transceivers. These devices cost much less than MIL-STD-1553 transceivers, making them more attractive economically.
So the next question is how SAE AS5652 will be implemented. Clearly, a sensible answer calls for intellectual-property (IP) cores in combination with FPGAs. Numerous arguments favor the IP core/field-programmable gate-array (FPGA) approach.
IP AND FPGAs
Unlike an application-specific integrated circuit (ASIC), an IP core can be downloaded easily into a FPGA. The FPGA itself is available in many densities, typically measured in logic units or gates. FPGAs come in many form factors, providing a broad range of available I/O pins. FPGAs also can provide internal memory.
For example, current state-of-the-art FPGAs from Xilinx have approximately 10 times more capacity than they did three years ago, with up to 6 million system gates. They also run at higher internal speeds. The IP cores can be predefined, and tested functions can be easily dropped into an FPGA design as well.
IP cores can greatly reduce the matter of obsolescence, which is crucial in any avionics design. That's because designers aren't tied to one specific part, or even one FPGA manufacturer. This is in stark contrast to sole-source, specialized-protocol ASICs and processors that could be discontinued at any time.
Production and lifecycle costs have continued to drop, and FPGA prices have acquired a proven history of declining dramatically over the life of a program (see the figure). Meanwhile, ASICs may increase in price over a long production run. In fact, many avionics systems already have an FPGA built into their design, and an EBR/MIL-STD-1553 core instance can easily fit in an existing chip or into a denser chip of the same family.
A soft, reprogrammable solution is desirable for line replacement units (LRUs) that are to be designed for several airframes—or for a base design meant for multiple uses. A multi-aircraft LRU demands a flexible, programmable design since several U.S. Air Force and NATO airframes have bus protocols that vary significantly.
Some have implemented extended data-set addressing through special subaddress or mode code protocols. Numerous fixed-and rotary-wing aircraft implement a mixture of older MILSTD-1553A and MIL-STD-1553B LRUs, requiring the bus controller and bus monitor to be able to handle different protocols. This means they also would be highly receptive to the proposed SAE AS5652 bus system.