Low-Power FPGAs

How do the various field-programmable gate-array (FPGA) technologies rank with respect to standby power consumption?

The three mainstream FPGA approaches significantly vary in static and standby power consumption due to the differences in the configuration technologies employed within the chips ? volatile static RAM cells, reprogrammable flash-based nonvolatile memory cells, and antifuse, metal-to-metal one-time programmable nonvolatile programmable elements (Fig. 1).

Static-RAM-based FPGAs consume the most standby power. Many transistors form all the SRAM cells used in the lookup-table memories that configure each logic block. The millions of transistors implemented in these blocks permit large amounts of leakage current. Thus, the SRAM-based FPGAs have a significant standby current ? typically tens of milliamps.

Flash-based FPGAs typically use less than 25% of the transistors needed to configure the logic versus the SRAM configuration scheme, because only a single flash transistor serves as the configuration element. So, leakage currents can be considerably smaller than SRAM-based FPGAs. Typical standby currents range from 1 to 10 mA.

See Figure 2

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