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Low-Power SERDES FPGAs Save Power

Lattice Semiconductor’s LatticeECP3 FPGAs target the midrange sweet spot needing high-speed serializers/deserializers (SERDES). The 65-nm FPGAs deliver 3.2-Gbit/s SERDES with XAUI jitter compliance. The SERDES are grouped in blocks of four, but they can handle independent protocols including PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO, and Gigabit Ethernet. The chips are designed for communication chores and include up to 7 Mbits of on-chip RAM plus 800-Mbit/s DDR3 support with built-in read/write leveling. The 1-Gbit/s low-voltage differential signaling (LVDS) I/O incorporates input delay blocks, allowing direct connection to high-performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The 500-MHz, 36-by-36 multipliers can be cascaded with 54-bit arithmetic logic units (ALUs) utilizing only more efficient hard-core logic. Lattice Semiconductor’s Simultaneous Switching Output (SSO) Design Planner augments the updated ispLever IDE. The LatticeECP3-70 with 67k lookup tables (LUTs) and a dozen SERDES costs $35.


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