EE Product News

Physical Synthesis Tool Targets High-End FPGAs

Designers can expect to achieve up to 40% performance improvements over traditional synthesis alone, it's claimed, with Amplify Physical Optimizer, touted as the industry's first physical synthesis tool for programmable logic devices. The core synthesis algorithms are leveraged to address the challenges associated with high-density programmable-logic designs for high-performance communications and multimedia applications. The tool merges physical design characteristics with synthesis in order to achieve optimum circuit performance. The physical synthesis tool enables optimum performance by allowing the user to assign physical constraints after HDL source code compilation, but before mapping, where maximum hardware performance can be achieved. Physical synthesis techniques, such as interconnect-based logic optimization, automatic logic replication and boundary optimizations on critical paths further improve performance without changing the HDL source code. Pricing for the synthesis tool begins at $25,000.

TAGS: Digital ICs
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