Today's megagate FPGA densities permit full digital system implementations. Still, many of these systems also require a reasonable amount of analog capability to complete the full system solution. These systems typically need a handful of analog components, like op amps, comparators, and analog-to-digital and digital-to-analog converters.
The Fusion mixed-signal FPGA architecture from Actel eliminates those components so designers can implement a true single-chip system. Actel will bring this architecture to market by early next year.
The Fusion architecture combines configurable analog peripherals, flash memory, and a multi-megagate FPGA fabric on a single chip (see the figure). The analog functions will leverage the high-voltage transistors available as part of the embedded flash-memory process used for the FPGA configuration data storage.
Based on the company's ProASIC 3 FPGA fabric, the FPGA portion of the Fusion devices will be able to deliver clock speeds of over 150 MHz on datapath logic. Soft processors such as an ARM7 32-bit CPU or an 8051 MCU can be instantiated in the logic fabric, while complex analog functions can be implemented in the multiple mixed-signal analog peripheral blocks.
The ability to combine the analog and digital functions on the same chip takes advantage of flash processing, which includes a high-isolation triple-well process. This processing also can support high-voltage transistors to meet the dynamic-range needs of mixed-signal designs.
Fusion peripherals will include hard analog intellectual property (IP) and hard and/or soft digital IP. The Fusion technology also will give designers new levels of flexibility by enabling them to easily reconfigure analog block settings to perform widely different functions by simply downloading data from embedded flash memory.
Peripherals will be able to communicate across the FPGA fabric using a layer of soft gates that are part of the Fusion Backbone. More than a common bus interface, the backbone integrates a microsequencer within the FPGA fabric. It will configure the individual peripherals and support low-level processing of peripheral data. Designers will be able to implement their own IP or leverage library blocks in the FPGA fabric. Dubbed Fusion Applets, these blocks will be available from Actel and its partners.
To support the Fusion FPGAs, Actel is developing multiple tool innovations that will maximize designer productivity. The tools will extend the company's established Libero integrated design environment. The tool extensions will add a comprehensive hardware/software debug capability as well as a suite of utilities to simplify development of embedded soft processors such as the ARM7 and 8051