Scaleable Million-Gate FPGAs Take On System-Level Designs

Representing an FPGA platform for addressing system-level designs, the Virtex FPGAs offer densities of up to 1 million gates. A 300,000-gate version is also available. The chips offer built-in capabilities that include solutions to chip-to-chip communication needs in spite of multiple I/O standards, numerous clock signal synchronization inside and outside the FPGA, and management for a variety of memory requirements.Virtex FPGAs are designed in as main system components in applications that previously called for ASICs, specifically standard cell-based devices. Some examples are: 66-MHz/64-bit PCI applications; OC-3, OC-12 and OC-48 communication equipment; next-generation network equipment; satellite base stations; high-performance graphics editing machines; massively parallel compute engines; and more. The chips' architecture is scaleable from 50,000 to 1 million system gates. The company's Alliance series 1.5 software delivers timing-driven place-and-route tools capable of compiling 200,000 gates/hour.