Structured ASICs Deliver Pin-Compatible FPGA Replacements

Although large FPGAs are popular when designers create system prototypes, they're often constraining in production due to high per-unit costs. The arrival of a lower-cost, pin-compatible solution for the latest 1.5-V generation FPGAs looks to smash through that barrier.

The XPressArray II family of mask-programmed structured ASICs, crafted by AMI Semiconductors, will basically take over when systems go into production. The company estimates that the family can reduce development costs by up to 70% with just a three- to four-week prototyping cycle.

The structured arrays are fabricated in a 150-nm process. They use five levels of metal for customization. (A sixth level is applied when flip-chip packaging is used.) Logic functions can operate at clock speeds of up to 210 MHz. Block RAMs access at speeds as high as 330 MHz. And, I/O pins will deliver data at rates of up to 1 Gbit/s using low-voltage differential signaling (LVDS) at 2.5 or 3.3 V.

I/O pads on the XPressArray handle a wide range of signaling requirements, providing LVDS, PCI-X 2.0 Mode-1 and Mode-2, and double-data-rate memory support. The pads also can be configured for low-voltage CMOS buffering at 1.5, 1.8, 2.5, and 3.3 V; low-voltage transistor-transistor-level buffering for 3.3-V signals; and GTL, GTL+, HSTL Class 1, 2, 3, and 4, low-voltage PECL (input), SSTL2 Class 1 and 2, and other signal interfaces.

Two versions of the XPressArray II family were designed to replace the XC2VP7 and XC2V4000 FPGAs from Xilinx. Another version aims to replace Altera's EP1S40 Stratix devices. The X2P528-FF672 packs 200,000 ASIC gates, 810 kbits of RAM, and 396 I/O pads. The larger X2P846-BF957 packs 690,000 ASIC gates, 2.2 Mbits of RAM, and 684 I/0 pads. The Altera-compatible X2P1148-BG1020 contains 470,000 ASIC gates, 3.4 Mbits of RAM, and 733 I/O pads. The two Xilinx-compatible devices will replace Virtex II and Virtex II Pro FPGAs, while the Altera-compatible unit will substitute for APEX-II and Stratix family FPGAs.

Nonrecurring engineering charges for the XPressArray II chips start at $85,000 for the X2P528 and increase to $100,000 and $150,000, respectively, for the X2P846 and X2P1148. In 50,000-unit quantities, the X2P328, X2P546, and X2P1148 mask-configured arrays cost $40, $105, and $240 each, respectively.