Electronic Design

Synthesis Tools Come Of Age For FPGAs

As FPGAs continue to increase their gate counts, the time-to-market window seems to only get smaller. Today, FPGAs have achieved complexities of three million or more gates, and FPGA vendors are predicting complexities of 12 million gates by 2003. Those wishing to employ such devices face many engineering challenges in order to optimize the designs and still meet their narrow market windows.

A key issue for designers of these "mega FPGAs" is timing delays, explains Jeff Garrison, the director of marketing for FPGA Products at Synplicity Inc., Sunnyvale, Calif. Unfortunately, the same fine-line technology that provides the high density and high speed on the FPGAs, brings with it a problem that has long plagued the ASIC world—timing delays. Once dominated by logic, timing delays are now largely set by the interconnections between logic. As a result, critical circuit timing, which often hinges on short block-to-block interconnections, remains an uncertain factor in an FPGA until after placement and routing.

"In order to take full advantage of today's FPGAs," Garrison continues, "Designers must be able to anticipate and correct for the effects of interconnect delays easily and early in the design flow. Time-to-market pressures alone demand it. But with interconnections constituting 70% to 80% of the delay, there has been no way to anticipate, prior to placement and routing, whether critical timing requirements will be met."

The solution to this problem requires the use of FPGA-based physical synthesis technology. Physical synthesis factors a design's physical characteristics into the synthesis process. During synthesis, a design is optimized and implemented based upon not only traditional timing constraints, but also physical constraints. The nature of the FPGA architecture makes it possible to perform physical optimization techniques during synthesis—for example, moving registers across regional boundaries to increase performance.

In addition, physical synthesis offers significant productivity as well as performance advantages to FPGA designers. By using physical constraints during synthesis, designs result in more accurate timing estimation, which eliminates time-consuming and tedious design iterations typically required with gate-level synthesis. Likewise, physical optimization during synthesis makes it possible to physically optimize a circuit for the best possible performance. FPGA physical synthesis forms the critical link between state-of-the-art programmable technology and designers seeking to leverage its unique advantages.

Another key issue for the design of high-density FPGAs is team design. At one million or more gates, an entire team of engineers is required to complete a project. "This," explains Garrison, "Brings its own set of problems including the challenge of optimizing across the boundaries of a partitioned design." Complete autonomy between team members to independently design, assign timing constraints and synthesize their portion of the design creates a timing challenge for the mega FPGA. Designers must be able to work in parallel on different portions of a design without having to guess in advance where the critical paths will lie. This requires design tools that can control the physical hierarchy. Using physical synthesis, designers can create a new physical hierarchy when a timing problem is found, saving weeks of iterations and enabling the team to meet its engineering schedule.

It also is unrealistic to assume that design teams will design two to three million gates from scratch. They must use various forms of intellectual property (IP). Depending upon the various IP sources—either internally developed or purchased commercially—the code might be in Verilog and/or VHDL. At present, the challenge is to mix these languages and still be able to optimize the design through synthesis. Clearly, the ability to handle multilanguage code is critical as the gate count escalates.

Fortunately, FPGA design technology is evolving to accommodate the needs of designers and is enabling these mega FPGAs to provide the performance, density and flexibility that the industry expects. This will allow designers to meet their time-to-market demands as gate densities continue to increase.

For more about Synplicity, check out the company's web site at www.synplicity.com.

TAGS: Digital ICs
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