The Vertical Cavity Surface Emitting Laser (VCSEL), a relatively new technology that emits light perpendicular to the substrate, offers many advantages over traditional lasers. But of the advantages, none is more profound than the fact that VCSELs can be tested and qualified at the wafer stage.
VCSELs have many intrinsic properties that allow for simpler fabrication, lower cost, and easier integration. As a result, they are a suitable laser source for a variety of fiber-optic applications and have become the preferred choice for datacom gigabit speed optical links at 850-nm wavelengths. In a similar fashion, it is predicted that 1,310-nm and 1,550-nm VCSELs will revolutionize optical component design for the telecom market.
Unlike VCSELs, all side-emitting lasers must be cleaved, polished, and coated before the first test/qualification stage. Not only does this add cost, but also sophisticated pick-and-place machines must handle the individual chips at the remaining stages.
Without the need for these extra stages, VCSEL devices can be tested and qualified on the wafer while the wafer is still intact. Typically, the measured data for all devices on a wafer is analyzed to give linearized light vs. current (L-I) and current vs. voltage (I-V) curves to determine threshold, slope-efficiency, diode knee, and series resistance (Figure 1).
Even though VCSELs already have a clear, intrinsic testing advantage, further improvements can help photonic component manufacturers minimize the overheads at the wafer test stage. Figure 2 explains the test overheads. It starts with the time taken by the wafer handler to move from one device on the wafer to the next. Although this can vary from handler to handler, a typical figure is 800 ms. Having moved the wafer onto the probe contacts, it is normal to use this contact pair to verify contact integrity to the wafer pad by measuring a low resistance through the pair. Kelvin contacts typically are used to eliminate errors caused by a voltage drop in the system wiring.
Once this is verified as correct, the LIV scan can start. For VCSEL devices, it would be typical to run a scan of 100 points from 0 to 10 mA in 0.1-mA steps. At each point, the voltage drop across the diode would be measured using the Kelvin connection plus a measurement of optical power from the wafer probe-mounted photodetector.
In total, the overall test time for a typical VCSEL wafer with 10,000 devices would be 2 s × 10,000 = 5.5 h. The challenge is to make significant improvements on this time. Figure 3 shows the sequence timing between stimulus and measurement.
So what’s the secret? Speed improvements come from three basic sources:
- The capability of the analog output to drive high inductive or capacitive loads. Usually, such an instrument would have a very slow output stage. However, an analog proportional, integral, derivative (PID) control loop can optimize the output settling time. This allows the output to achieve its programmed state in the shortest possible time without the risk of overshoot. In addition, a fully floating output with respect to system ground eliminates ground loops that so often introduce noise and inaccuracy.
- Incorporating a sequence engine to take control of the LIV sweep. It controls the exact timing of each step in real time and allows timing to change from step to step. Part of this functionality is achieved by using the PXI local trigger bus of the PXI system (the PXI specification allows for slot-to-slot trigger lines that are inherently fast) for board-to-board communications. Measured data is stored in local onboard memory.
- PXI modules communicating with the controlling PC via the 33-MHz parallel bus and allowing large blocks of data to be transferred in a few milliseconds.
Applying this technology to VCSEL test and qualification yields the following results:
- The LIV sweep starts from zero so the steps from 0.1 to 1 mA produce low output levels from the wide-area photodetector.
- The detector exhibits high intrinsic capacitance so a longer settling time must be programmed with each step.
- The sequence engine allows each of the first steps to be programmed with a decreasing delay until the point where each cycle has a minimum delay of 100 µs.
Taking the previous example where each wafer has 10,000 devices, the overall test time is 0.9 s × 10,000 = 2.5 h or a 120% increase in productivity.
With the wafer handler now contributing to 90% of the overhead, it makes sense to examine the possibility of testing multiple devices in a single scan. Although probe-card complexity is increased, the act of probing four devices at one time is not seen as a technology challenge. Switching between Kelvin connection test and multiple LIV sweeps on each block of four diodes is accomplished by using a high-speed multiplex switch card. In this case, the results show the test time to be 1.0 s × (10,000/4) = 0.7 h or approximately a 700% increase in productivity.
Figure 4 illustrates the test setup. This configuration is not limited to four diodes. The switch matrix card, as shown, can accommodate up to 19 diodes in a single probe sequence.
About the Author
Robin Agnew is vice president of business development at PX Instrument Technology. Before joining the company, he held senior positions at Teradyne and Innovate. Mr. Agnew earned a diploma in telecommunications from Coventry, U.K. PX Instrument Technology, Unit 32 Beechwood Close, Boghall Rd., Bray Co. Wicklow, Ireland, 011 353 1 2864221, e-mail: [email protected]
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August 2002