One cost-effective solution is an open-architecture ATE (OA-ATE) system that allows specialized semiconductor manufacturers to specify the instrumentation they require. OA-ATE must incorporate these vital elements:
- An industry-standard bus structure.
- Compatibility with industry-standard data formats.
- Browser technology to access and control resources.
- A modular hardware and software structure to enable reconfigurability.
- Partitioned test supported by ATE and EDA tools.
Incorporating these elements puts in place a number of characteristics that influence and substantially improve time-to-market and cost-of-test. Table 1 lists some of the more important advantages.
| Conventional ATE | OA-ATE | Impact | |
| Instrumentation | Limited variety High cost |
Large number available (>1,000) Shared development cost |
Flexibility; up Cost: down |
| Software | Tester specific Proprietary Monolithic |
Hardware-independent Industry standard Modular |
Improved IP reuse Trained engineers available Cost: down Time-to-market: down |
| Resource libraries | Not available | Test libraries Tool libraries Probe pad and package libraries |
Consistency improved Time-to-market: down Cost: down Expertise required: down |
| Configurability | Limited by available instruments Complex process for hardware and software |
Universal pin card slot Modular hardware and software Industry standard bus Plug-and-play instruments |
Flexibility improved Cost: down Time-to-market: down Depreciation life: up |
| Calibration | External instrumentation required Full recalibration required after reconfiguration |
NIST-traceable internal calibration on most instruments Calibration required only for added resources |
More reliable calibration Hours saved with each reconfiguration |
Table 1. Conventional vs. OA-ATE
Costs
The 2000 International Technology Roadmap for Semiconductors (ITRS) forecasted ATE costs in excess of $20 million. This was reduced in 2001 to approximately $6 million as the financial impact of design-for-test (DFT) technology was recognized. This is a marked improvement but still inappropriate for devices with an average selling price under $2.
The ITRS identifies several approaches that alter test strategy cost in an effort to arrest test-cost escalation. For example, the constantly increasing frequency, accuracy, and I/O count in integrated circuits (ICs) are being addressed by DFT solutions that may be successful for high-volume digital devices but do not solve the industry cost problem.
Many ATE systems still list above $1.5 million, and test times are escalating as device size and complexity increase. These ATE systems are not unreasonably priced since their architectures incorporate expensive, custom-engineered subsystems. They remain large and power hungry because of the special-purpose bus structures used to deliver the bandwidth and high thermal density used to provide the required accuracy. In addition, the traditional ATE architectures fail to take advantage of lower-cost industry-standard instruments.
Industry-Standard Instrumentation
The instrumentation industry supports a number of standards for bus structures and form factors, including PCI and PXI. By using instruments conforming to these standards wherever they can be implemented, ATE manufacturers can reduce development time and system costs.
Other economic advantages are associated with conformance to industry standards. Development and maintenance of software, availability of advanced programming tools, and ease of intellectual property reuse all can be improved. Over time, these factors may be even more important than ATE cost-of-ownership but are not quantified here.
Product life cycles have decreased significantly, driven by consumer demand and enabled by advances in design tools and acceleration of fabrication technology. These reduced cycles require shorter time-to-market, and production test constraints often are the gating issue.
EDA tools providing automatic test pattern generation (ATPG) have made progress in memory and logic testing, but most SOC ICs today incorporate analog elements and specialized circuits not supported by existing ATPG technology. Custom load-board solutions often are required for complex mixed-signal parts, making the task more difficult and time-consuming.
In general, the ATE industry has been slow to adopt the promising technologies that enable reductions in time-to-market required by the IC manufacturers. EDA tools already incorporate co-design of circuits, packages, and test strategies. Both ATE and EDA tools also must enable test partitioning between various DFT approaches and traditional ATE.
These features must be supported to meet the imperatives of shorter time-to-market and lower cost-of-test. The closed architectures and one-dimensional EDA tools that dominate the landscape today will not be viable in the new generation of ICs.
User Reconfigurability
Complex circuits must use DFT techniques to control test cost. The initial validation of any new design uses conventional ATE for device characterization and verification of DFT techniques. This ATE is expensive and inconsistent with cost-effective production.
Also, conversion to a lower-cost ATE system for production following characterization is costly and time-consuming. A better solution is a configurable system that can be quickly altered to meet either device characterization or production test.
The architectures for conventional ATE and reconfigurable ATE are shown in Figure 1 and Figure 2, respectively. Reconfigurability allows rapid change of instrumentation, disturbing only the signal paths that require resource changes. This makes it practical to use device-specific tester configurations that always deliver the lowest cost because no unused resources are in the system.
The Internet and virtual private networks (VPNs) make it possible for a virtual semiconductor company without fabrication facilities or test and assembly operations to have timely access to information previously enjoyed only by independent device manufacturers. Internet-compatible, browser-enabled ATE makes data available anywhere in real time with only Internet latency. This supports more rapid problem identification and resolution (Table 2).
| Conventional ATE | Internet-Enabled ATE | Impact | |
| Distributed Test | Only accomplished through expensive third-party tools | Fully supported through available tools using a VPN | Better data availability Flexibility in resource management Lower cost |
| Yield Enhancement | Expensive third party | All data from all systems available in real time | Rapid identification of yield loss or other inefficiencies |
| Diagnostics/Repair | Local to the system | Can be run locally or over a VPN | Improved availability Remote repair |
| Configurability | Requires ATE specialist with device knowledge | On-line configuration can determine instruments needed | Reduced engineering expertise required Flexibility improved |
Table 2. Internet-Compatible Browser-Enabled vs. Conventional ATE
Case Studies
The following case studies are based on actual results by ATE users rather than system specifications. In some cases, the ATE specifications defined for ideal conditions were not achieved in actual testing.
Data Converter
A 14-bit, high-speed analog-to-digital converter (ADC) is typical of the emerging ATE challenges. The test requirements were not met by conventional ATE that was evaluated because it lacked the desired measurement resolution, could not demonstrate the required noise floor, or both. Table 3 provides a comparison of conventional and OA-ATE in this application.
Proprietary instrument
Industry-standard instrument
Table 3. 14-Bit, High-Speed Data Converter
Probe Test for Characterization and Device Debug—243 Pins
High-Precision Differential Stimulus
High-Precision Calibration
Trim Algorithm Included in the Test Program
Numerous Control and Measure Points
Cost, size, and power advantages for OA-ATE are perhaps the most obvious but not the most important. Specialized instrumentation required in the characterization phase was easily developed and integrated into the OA-ATE, taking advantage of hardware and software infrastructures to reduce cost and time-to-market. Providing these resources via load boards costs more and takes longer.
SIP Devices
The emergence of SIP configurations poses similar challenges. In this case, the four-chip SIP required 50 A and 900 V. These are not available with conventional ATE pin cards, so a costly load-board solution was implemented, which delayed test-program development and increased total cost. The conventional ATE solution was functionally adequate but hampered by high cost and long execution time. Introducing OA-ATE to the problem enabled delivery of all test resources from pin cards.
The size, power, and cost of the system were reduced significantly, but the dominant advantage was improved test time. The characteristics contrasting the two solutions are listed in Table 4. These examples indicate that conventional ATE gets the test job done but at a slower pace and a higher cost than with OA-ATE.
| Parameter | Conventional ATE | OA-ATE |
| Load Board Complexity | Special circuits for high-voltage and high-current stimulus | No special circuitry |
| Test Time | 43 s | 15 s |
| Footprint and Weight | >20 ft2; >1,000 lb | < 6 ft2; < 100 lb |
| Power Requirements | > 2 kW | 600 W |
| System Cost | $550,000 | $165,000 |
| External Instrumentation | High-voltage supply High-current supply |
None; high-voltage/high-current plug-in cards currently available |
Final Package Test—43 Nodes
Circuit Elements Tested Include MOSFETs, IGBTs
High Current: 80-A Peak
High Voltage: 900-V Peak
Leakage Current: <10 nA
The application of OA-ATE delivers the following benefits in advanced SOC and SIP testing:
- A drop in per-transistor test costs.
- An order of magnitude reduction in test-related time-to-market delays.
- Efficient partitioning of test through device and test co-design.
- Insertion of home-grown hardware and software components supported by open-architecture industry standards.
About the Author
W. R. (Bill) Bottoms is founder and chairman of the board of 3MTS. Dr. Bottoms was appointed to the faculty of Princeton University in 1969 and since then has served as the initial president of the Semiconductor Equipment Group of Varian Associates and chairman and CEO of Credence. Prior to joining Credence, Dr. Bottoms spent more than 10 years in the venture capital industry as a partner of APA. Third Millennium Test Solutions, 2160 Lundy Ave., Suite 110, San Jose, CA 95131, 408-435-1788, e-mail: [email protected]
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October 2002