Paradigm shifts in technology initiatives don’t come without their skeptics, as is the case with the DoD’s Hardware/Software Convergence Initiative. Aimed at developing a common, modular hardware architecture across C4ISR and EW systems, this program combines separate efforts initially undertaken by the U.S. Army under CERDEC (CMOSS), the U.S. Navy under NAVAIR (HOST), and the Air Force under AFLCMC into one, cohesive COTS-based, open standards initiative.
Now managed entirely under Sensor Open Systems Architecture (SOSA), this collection of open architecture standards provides reconfigurable, upgradable, and cost-effective C4ISR capabilities in deployed platforms across sensor applications throughout all major military branches. Using OpenVPX as its basis, it’s setting the standard for interoperable systems across several defense branches to improve subsystem SWaP, enable rapid technology insertion, and promote reuse.
It’s important to understand how both OpenVPX’s history in military environments as well as its pedigree as a ratified industry standard can help facilitate this widespread, and seemingly complex, undertaking to break from the old method of costly proprietary computing systems.
Below, some common misconceptions about OpenVPX are dispelled, and we examine how it can provide the right environment for the SOSA initiative
1. The card isn’t going to be compatible.
This depends on whether the target backplane is a VITA 65.0 standard development backplane or a customer-driven deployed backplane. The VITA 65.0 standard development backplanes have very simple topologies that are compatible with lots of cards. Actual VPX system backplanes have much more complex topologies with many I/O signals.
Consequently, these backplanes are usually designed for specific cards and map to the unique I/O mapping of one VPX module. With the development of fully defined SOSA VPX slot profiles, even complex backplanes will be wired for standard slot profiles, and the result will be more modules compatible with any given backplane implementation.
2. I won’t be able to get enough power.
Enough power is no longer the problem—it’s properly cooling the amount of available power. In the past, VME64x and CompactPCI cards could each typically draw no more than 150 W from a backplane slot. As large FPGA silicon became available from companies such as Xilinx and Altera, the power needs of an individual card exceeded the amount of power that a card could draw because the pin assignments and contact design did not allow for more power.
3U VPX cards can draw over 270 W and 6U cards could draw over 380 W. It’s unlikely that VPX systems will ever be limited due to power availability. And, new cooling standards are being released to allow more of this VPX power to be used in future systems.
3. I’ll need a custom backplane.
One of the main criticisms of the VPX architecture, and a fair one at that, is that it doesn’t consider all of the other VPX features that have made the architecture so desirable. The mandate for custom backplanes is, therefore, being tolerated by designers.
A new solution designed to meet the need for fully customized VPX backplanes is on the horizon. Pioneered by hard-working technical groups under SOSA, emerging standard profile definitions will eliminate much of the need for VPX backplane slots to be wired for specific, unique VPX modules when using SOSA conforming plug-in cards (see figure).
This 3U OpenVPX backplane, which serves as an integration platform for modules addressing the DoD’s CMOSS initiative, provides the foundation to create systems optimized for performance, with reduced SWaP and lower lifecycle costs for rapid technology insertion.
4. I can’t run 10 Gb/s out of the backplane.
For some time, PCIe Gen2 and 10GBase-KX4 were thought to be the fastest protocols that could be reliably passed to I/O devices through cables, which plugged into VPX backplane RTM connectors. Recently, a new approach that utilizes new backplane materials, together with improved via design, has pushed this limit to PCIe Gen3 and 40GBase-KR4. It’s highly likely that a new, backward-compatible VPX connector may even allow these higher speeds to be exceeded in the near future.
5. VITA 65 may not meet all my design needs.
This was most likely said by those who haven’t reviewed the current list of available features added to VPX. In fact, it’s hard to imagine an application that could not be implemented within the standard. VPX is rugged and supports two card sizes. Some of the new features include miniature coaxial backplane feed-thru, backplane optical ribbons, radial clocks, 25-Gb/s channels, rugged vibration-resistant connectors hybrid topologies, XMC sockets, as well as VITA 57.4 FPGA mezzanines that support 28-Gb/s links between the base board and the mezzanine. The coaxial modules now available are causing an explosion of new applications.
6. All of the VPX connectors are expensive because they are sole-sourced.
OpenVPX was built specifically with the goal of eliminating single-source pitfalls. To date, there are three suppliers of intermatable backplane connectors, one of which already offers three different versions of the VITA 46 connector. All versions are forward and backward-compatible.
The connectors cost more because of the performance they provide. These high-density, high-speed connectors allow space for XMC/PMC mezzanine sockets and fit within the 3U and 6U 160 Eurocard packaging formats. In addition, there are space-qualified, high-vibration-resistant, footprint-compatible VPX backplane/daughtercard connectors. Paying for the benefits of performance enhancement is true for whatever architecture you choose.
7. The multi-connector is limited to 12 Gb/s.
Although the current connector supports signaling up 12 Gb/s, which is just beyond PCIe Gen3 and 10Base-KR Ethernet, a new backward-compatible version of the same MultiGig connector is being standardized and will support Ethernet lanes up to 25 Gb/s and Fat Pipes (FP) supporting 100GBase-KR4. This connector is both backward- and forward-compatible, so that old cards can be used in the new backplanes and new cards will be usable in the old backplanes. However, the speed will always have to be negotiated down to the least capable element in the path.
8. I can’t inspect VITA 66.1/66.4 optical modules in the field.
There’s now an inspection card for 6U VPX conduction-cooled chassis that will automatically both inspect—and clean—VITA 66.1 optical modules installed in either the J3 or J6 position in a 6U VPX backplane.
Independent of the VPX system, this tool is tethered to a laptop running software that will execute multiple inspect/clean/inspect cycles until all of the fibers meet inspection requirements. Then, a new card can be inserted into the fully inspected VPX slot in the field. The hope is that this equipment will be extended to 3U VPX slots that are either in accordance with AV 48.1 or AV 48.2.
9. Isn’t air flow-through the same as convection cooling?
Not at all. Three different cooling methods are actually included in OpenVPX that all depend on forced air. While technically not “new,” since these methods have been used with VME for years for demanding applications, they’re now standardized. Check out VITA 48.5, 48.7, and 48.8. Each offer advantages over conventional forced air, because each method allows air to be directed specifically where it’s needed.
10. I heard that the VITA 46.11 IPMI-based system manager isn’t really secure enough for cybersecurity.
Your concerns have been heard, and the HOST and SOSA working groups are really beefing up the System Management approach and adding new capabilities, such as large file transfer support and IPMI 2.0 security. These two working groups are supported by a large team at the University of Georgia Research Institute, the U.S. Army, U.S. Air Force and NAVAIR, as well as individual companies and SBIR (Small Business Innovation Research) award winners. It’s a level of cooperation never seen before.
11. Can an intermediate frequency be shared between radio cards in a VPX backplane? I’ve heard that there isn’t sufficient isolation.
It’s true that the MultiGig signal pins may not provide sufficient isolation between pairs to distribute an intermediate frequency between radio cards. However, VPX slots now support a variety of coaxial interfaces that can distribute an intermediate frequency or very precise clocks such as Precision Time Protocol (PTP) and Network Time Protocol (NPT).
VITA 67.3 only defines the opening in the backplane, the mounting holes, and alignment pins, and supports several sizes of modules as well as a growing number of unique contact configurations, including mixed coax and optical interfaces. These 67.3 modules are easily removed and replaced on the backplane, so reconfiguration is possible.
VITA is working to standardize additional contacts, but users are already employing coaxial contacts such as SMPM (multiple suppliers), nanoRF (TE currently), and SMPS (SVmicro). SMPM (many vendors) is lower density, but it supports the greatest variety of backside cable options including flexible, semi-rigid, and right-angle terminations. Some SMPM configurations are already standardized within VITA documents.
We’re only addressing the backplane side because 67.3 was developed to support direct launch from the daughtercard mezzanines, though cable can also be used. Furthermore, VITA 67.3 modules can support new higher-density nanoRF and SMPS contacts. Half-size 67.3 modules with as many as 12 coaxial contacts are already in the marketplace and being used. The denser connectors only support flexible cables presently. These can be used to distribute the precision clocks already mentioned. You can also see a mix of SMPM and either nanoRF or SMPS contacts as well as optical MT ferrules combined in a single 67.3 module.
Michael Munroe is Technical Product Specialist at Elma Electronic Inc.