Lattice Semiconductor’s CrossLinkPlus is designed to handle interface conversion, including support for MIPI virtual channels (Fig. 1). The chip will be useful to bridge between a peripheral’s interface and one available on a host.
1. CrossLinkPlus wraps hard MIPI interfaces around a 6K LUT flash-based FPGA.
FPGAs have been used for this function since the onset of their development. The big difference tends to be the amount of hardened interfaces that are included with the FGPA. The alternative is to use a soft interface built using the FPGA fabric. There’s also the issue of PHYs that can be built-in or off-chip. Integrating hard interfaces and PHYs on-chip reduces the footprint, but it limits the chip to supporting the hard interfaces. On the plus side, the latest interfaces like MIPI D-PHY are becoming more readily available on hosts and devices.
CrossLinkPlus FPGAs come in a compact 3.5- × 3.5-mm package. They also consume less than 300 µW of power. Including hard interfaces on-chip makes this small, low-power solution possible while handling MIPI interface speeds up to 6 Gb/s.
A range of interfaces are supported, including MIPI D-PHY, sub-LVDS, and OpenLDI (Fig. 2). The chip can handle one-to-one transitions for those interfaces that support individual channels. It can also manage multiple channels when using MIPI virtual-channel support. This allows a host to handle multiple MIPI-based input devices using a single MIPI interface or drive multiple devices, again, with a single MIPI interface.
2. CrossLinkPlus can handle interface conversion in addition to muxing/demuxing of MIPI channels and virtual channels.
The FPGA allows the data flowing through chip to be modified. The Lattice Diamond FGPA development software can take advantage of existing IP, as well as be used to create custom IP for the FPGA fabric. The flash-based FPGA allows for fast startup. The chip also features GPIO and I2C/SPI interfaces.
