HyperTransport Releases I/O Link 2.0

The HyperTransport Consortium has released version 2.0 of the specification defining new enhancements to the HyperTransport I/O Link interface. The 2.0 release defines three new speed levels and a new mapping to PCI Express, an emerging I/O...
Feb. 16, 2004

The HyperTransport Consortium has released version 2.0 of the specification defining new enhancements to the HyperTransport I/O Link interface. The 2.0 release defines three new speed levels and a new mapping to PCI Express, an emerging I/O interconnect architecture. The three speed specifications define 2.0-, 2.4-, and 2.8-Gtransfer/s performance levels using dual-data-rate clocks of 1, 1.2, and 1.4 GHz, respectively. This boosts the maximum aggregate throughput of a HyperTransport interface to 22.4 Gbytes/s. The electrical protocols that support the new clock rates are backward-compatible with previous versions of the HyperTransport electrical specifications. The HyperTransport consortium licenses the technology royalty-free. For more information, go to www.hypertransport.org.

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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