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Electronic Design

Interconnecting Mini MEMS Spawns Max Challenges

Several novel processes help ease the problem of getting these tiny devices hooked up to other ICs

If you're looking for a challenge, try interconnecting microelectromechanical-systems (MEMS) ICs with conventional ICs and other MEMS ICs. If you've mastered that skill, move to the front of the line, because MEMS technology involves a high level of integration between many dissimilar functions.

Generally, it's about integrating electronic with mechanical functions. So what's considered the ultimate goal of such a process? It's a seamless integration of the MEMS structure onto the same CMOS chip as the circuitry with which it will interface.

Today's MEMS ICs may combine electrical and mechanical functions. In some cases, they include optical signals. Known as micro-optoelectromechanical systems (MOEMS), these devices use micromirrors to direct signals in high-definition TVs and, one day, may direct signals on the Internet. Another technology, silicon microchannels (microfluidics), will process gases, liquids, and nano-particles on lab-on-a-chip devices that will drive major medical breakthroughs.

Some conventional ICs now use through-silicon vias (TSVs) to interconnect chips into thinner 3D structures. Manufacturers are now developing processes that will open the door to TSVs with diameters ranging from 30 to 50 mm on 50-mm thin wafers with 300-mm diameters. Someday, TSVs also may be applied to MEMS interconnects.

Because a MEMS IC must reside in a cavity or other unrestricted space for free mechanical motion, it can't be packaged through conventional means. The chip must be capped or epoxy overmolded, though conventional over-molding isn't viable since the MEMS structure can't be "locked" in place. Moreover, the MEMS IC must be protected from contamination common to IC techniques. Residue from die sawing and the high-temperature effects of standard IC processes can be lethal for MEMS ICs.

Also, a MEMS IC can't offer any functionality on its own. It must be hooked up with additional electronic circuitry for signal processing and other functions, as well as processing circuitry, to make it useful. That's because a MEMS process differs from standard IC processes like CMOS. The supporting circuitry in nearly all MEMS ICs requires additional ICs, which leads to many possible interconnect implementations (see "MEMS Meets ASIC").

Due to the structural nature of MEMS devices, conventional polycrystalline silicon processing can't be used to integrate a MEMS device with a conventional IC. Polysilicon IC processing requires temperatures of 800°C and higher, which would compromise and destroy a MEMS structure. But low-temperature, back-of-the-line (BOL), silicon-germanium (SiGe) processes that can handle temperatures of about 400°C to 450°C make it possible to integrate MEMS devices on top of standard silicon-based electronics (see "Low-Temperature SiGe Processing Advances MEMS Integration,").

The use of improved capping materials is becoming more popular, with different techniques being employed to interface the MEMS device to another IC. Wafer- and device-level packaging often are used for the high-volume production of MEMS ICs, where the chip is packaged prior to the wafer-dicing step.

One method employs through vias and pads on the outside of the cap. In this case, engineers can use wafer-level processing that permits the sawing of both the cap material and the MEMS chip simultaneously. Such an approach yields a chip with few wire-bond pads on it.

Another approach is to create micro-vias and bring the MEMS pads to the bottom, put a regular cap on the MEMS chip with a little cavity, and then bond the chip. Many firms involved in 3D chip stacking are developing through-via processes to create silicon micro-vias. The microvias then are plated, which allows for passive chip stacking.

This can be performed at the wafer level with hermetic sealing, eschewing any secondary packaging steps. In fact, it's possible to package an entire MEMS chip at the wafer level (Fig. 1). This is sometimes called zero-level packaging. Once the cap is in place, the IC package can be handled using conventional IC processing. It can even be encapsulated by liquid dispensing or transfer over-molding.

VTI Technologies' glass-silicon capping wafer technology provides a large number of feed-throughs with very low parasitic capacitance, high isolation resistance, and reasonably low contact resistance. Silicon areas extend through a glass wafer from the contact areas on the top down to electrodes on the bottom. The bottom makes ohmic contact with the MEMS structure or acts as a planar electrode for vertical sensing or excitation. The top surface metallization also can be used for interconnection between feed-throughs and for rerouting.

Hermeticity is an important parameter when choosing the material to cap the MEMS IC's cavity. For high-level hermeticity, the cavity can use a transfer-molded capping material as well as a low-temperature co-fired ceramic (LTCC) package. But high-level hermeticity entails costs for many MEMS IC applications, such as consumer electronics.

Many MEMS IC manufacturers choose a less costly, near-hermetic approach using transfer-molded epoxy resins and non-hermetic plastic packages. This provides near-hermetic features that fall between a hermetic ceramic approach and a non-hermetic plastic approach. These companies use thermoplastics like liquid-crystal polymer (LCP), which deforms when heat is applied and then dries to a brittle state when heat is removed.

Thermoplastics are very stable and enable the use of low-cost injection molding that can withstand up to 300°C or more. They also feature good moisture absorption and can be melted and reused, allowing for recycling.

Thermoplastic usage isn't new. Ken Gilleo, president of ET-Trends, says thermoplastics have had a long and excellent record in biomedical applications like stents with drug-bearing polymers and medical implants. However, they've been mostly ignored for MEMS. The advantages and natural fit of thermoplastics for MEMS devices are so obvious to him that he believes someone must be developing them for MEMS.

Right now, the industry is moving toward wafer-level packaging, where the entire package is formed while the MEMS device is still in wafer format. Many MEMS experts believe this newly evolving methodology is an ideal approach, saying it streamlines and reduces the cost of the total process of integrating a MEMS IC with other ICs.

Successful examples have emerged. For instance, take Tessera's image-sensing chips, which use the company's Shellcase technology (see "Razor-Thin Package Sharpens Image-Sensing Applications,"). It's only a matter of time before MEMS ICs like pressure sensors, accelerometers, and other functions reap the benefits of wafer-level packaging.

The Tessera/Shellcase example represents the trend to stack ICs into thinner overall package structures. True 3D integration is another challenge, though. It requires interconnect methods that can reduce the average length of the interconnect wire to overcome performance-limiting factors when scaling ICs into thinner and thinner devices.

Tezzaron Semiconductor's vertical copper interconnect technology, SuperVia, is widely used in MEMS bonder/aligner equipment, as well as for the creation of unique substrates. According to the company, the scheme's copper-to-copper bond not only meets but also exceeds minimum strength requirements for interconnections. It's even stronger than a typical copper-to-silicon-dioxide (SiO2) interface.

Many MEMS IC manufacturers have successfully produced MEMS ICs with signal-conditioning circuitry using conventional IC processing. Many of these processes, however, are developed in-house or licensed from other companies that have perfected them.

Analog Devices pioneered the monolithic MEMS accelerometer over a decade ago using surface micromachining. Until then, all other MEMS devices were produced using bulk micromachining. ADI used a biCMOS process in which the MEMS structure sits side by side with the signal-processing circuit.

First, selective etching is employed in a standard IC photolithographic process. Then, a sacrificial oxide layer is deposited on a polysilicon layer. The resulting 3D MEMS structure is suspended above the substrate. The biCMOS process is used for the signal-processing circuitry (Fig. 2).

Akustica's monolithic CMOS MEMS microphone IC includes a metallization layer that's brought out and connected to a separately manufactured CMOS signal-processing circuit. One step at the end of the manufacturing process removes sacrificial oxide layers (Fig. 3).

SiTime and Bosch Sensortec have achieved commercial success with MEMS ICs and signal-processing circuits as well. SiTime uses a Bosch-licensed MEMS First CMOS process. As such, a MEMS timing circuit with temperature-compensation circuitry can be integrated into industry-standard packages (Fig. 4).

Discera also produces a MEMS timing circuit. But unlike Bosch and SiTime, Discera puts down the MEMS structure after manufacturing the CMOS signal-processing circuit. It most recently introduced a programmable two-chip MEMS timing circuit. The MEMS resonator is placed within a capped structure and a signal-conditioning ASIC interconnected via wire-bonds to the resonator structure using wafer-level processing.

One of the more successful commercial efforts for MEMS ICs has been Texas Instruments' digital-light-processing (DLP) technology, as implemented in TI's MOEMS digital micromirror device (DMD). The DMD IC forms the basis of home-theater, rear-projection, high-definition TVs with screen diagonal sizes of 60 in. or more. However, MOEMS are even more challenging to interconnect and package than MEMS ICs (see "Interconnecting MOEMS ICs,").

Interconnecting MEMS ICs is challenging enough. But it pales in comparison to interconnecting microfluidic MEMS, which require very specialized packages and circuit boards. Microfluidics go beyond MEMS ICs and their electron-based interconnect needs, requiring plumbing-like approaches to handle fluids, gases, and solids. On top of that, they often need fluidic connectors and couplings as well as optical pathways (Fig. 5).

The best method for interconnecting these microfluidic ICs is to use press-fit interconnects to microfluidic channels molded in polydimethylsiloxane (PDMS). First, a small hole is cored in the PDMS to access molded or buried microchannels with a tiny needle. Next, another needle is inserted into the hole to create a direct connection to the microchannel that requires no bonding or molding. The needles then can be easily removed and reinserted multiple times, since the seal is created purely by the compression of the PDMS around each needle.

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