Chip Packaging Blurs Lines Between IC Fabrication And Test
The key to packaging innovation often lies with production, where making component packages smaller may be inherently linked with making them more efficiently. Batch processing increases throughput and drives down package cost, which makes new, smaller IC packages more attractive. In some cases, the process exploits a new packaging technique that features smaller package size.
The batch concept is being applied to combine the steps of semiconductor wafer fabrication with chip packaging. Wafer-level processing does this for chip-scale packages. Batch techniques are also being employed to merge packaging assembly and test.
Increasing production efficiency is not merely the objective for packaging ICs, it's also the goal of all of the R&D aimed at system-in-package, 3D packaging, and other modular approaches to integration. Techniques already exist for making circuits "small at any cost." Now the focus is on achieving extreme miniaturization in high-volume applications.
Greater integration of packaging and test. Vendors such as Amkor (www.amkor.com) have already recognized that chip packaging and test are functions that can be integrated to achieve greater production efficiencies. And, the assembly and test equipment needed to parallel-process batches of chips at a time is here. Now it's up to packaging companies to work with their customers to adapt this technology to their needs to experience its benefits.
Greater use of high-density build-up organic packages for flip chips. Expect to see technologies like that recently introduced by Kyocera go into production this year. This technology promises to reduce flip-chip bump pitch to just 150 µm and, through the use of laser-drilling, achieve through-via pitches of 220 µm in the substrate's core. At the same time, it embeds conductors in the core with 40-µm lines and spaces.
Chip-scale packages will gain in popularity as more suppliers and customers master the fabrication and assembly of these components. Expect to see greater use of CSPs for analog ICs and discrete semiconductors.
Packaging for discrete semiconductors will increasingly offer footprints as small as 0.5 mm2. With companies like On Semiconductor (www.onsemi.com) introducing these low-cost plastic packages to the marketplace, expect designers to be lured away from current industry standards like the SC-79 and SC-75, which have footprints at least twice as great as the new packages.
New techniques for packaging power MOSFETs will significantly increase their power handling capabilities. In surface-mount packaging, expect designs that conduct heat away from the die more efficiently than even the bottomless SO-8.
Wafer-thinning techniques that produce ultrathin chips on the order of 10 to 30 µm will lead to the development of novel, paper-thin electronics. "Smart" labels using thinned transponder chips and screen-printed coils are one example that's already been demonstrated.
Thermal-management issues will resonate throughout the industry. The call will go out for designers with packaging expertise in high-power and high-temperature electronics. Engineering programs will expand the course offerings in this area by melding the relevant electrical and mechanical disciplines. An early effort in this area is already under way at the University of Maryland to create Web-based training that will provide students and working professionals with the essentials of mechanical design for high-power, high-temperature electronics.
At the system level, expect forced air cooling to become insufficient for many new applications and alternatives like liquid-based cooling and refrigeration to become necessary more often.